Takashi Kono

According to our database1, Takashi Kono authored at least 23 papers between 2000 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-ns Random Read Access and 7.4-MB/s Write Throughput at up to 150 °C.
IEEE J. Solid State Circuits, April, 2024

15.8 A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
An On-Chip DC-DC Converter and Power Management System Achieving Zero Standby-to-Active Transition Time in MCU.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022
A 40-nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200-MHz Random Read Operation and 7.91-Mb/mm<sup>2</sup> Density With Charge-Assisted Offset Cancellation Sense Amplifier.
IEEE J. Solid State Circuits, 2022

A 22nm 32Mb Embedded STT-MRAM Macro Achieving 5.9ns Random Read Access and 5.8MB/s Write Throughput at up to Tj of 150 °C.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age.
IEICE Trans. Electron., 2020

2019
A 65nm Silicon-on-Thin-Box (SOTB) Embedded 2T-MONOS Flash Achieving 0.22 pJ/bit Read Energy with 64 MHz Access for IoT Applications.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 24MB Embedded Flash System Based on 28nm SG-MONOS Featuring 240MHz Read Operations and Robust Over-The-Air Software Update for Automotive.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018
Overview of Embedded Flash Memory Technology.
Proceedings of the Embedded Flash Memory for Embedded Systems: Technology, 2018

Introduction to the January Special Issue on the 2017 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2018

2017
Embedded non-volatile memory system as an enabler of smarter world.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

Session 11 overview: Nonvolatile memory solutions.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C.
IEEE J. Solid State Circuits, 2016

7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Session 7 overview: Non-volatile memory solutions: Memory subcommittee.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170°C.
IEEE J. Solid State Circuits, 2014

2013
40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2005
Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories.
IEICE Trans. Electron., 2005

2004
A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM.
IEEE J. Solid State Circuits, 2004

2000
A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica.
IEEE J. Solid State Circuits, 2000

A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs.
IEEE J. Solid State Circuits, 2000


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