Syed Suhaib

Affiliations:
  • Virginia Tech, Blacksburg, Virginia, USA


According to our database1, Syed Suhaib authored at least 14 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
Domain-Adapted LLMs for VLSI Design and Verification: A Case Study on Formal Verification.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

2008
A Trace-Based Framework for Verifiable GALS Composition of IPs.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Formal Transformation of a KPN Specification to a GALS Implementation.
Proceedings of the Forum on specification and Design Languages, 2008

2007
Formal Methods for Intellectual Property Composition Across Synchronization Domains.
PhD thesis, 2007

Dataflow Architectures for GALS.
Proceedings of the Third International Workshop on Formal Methods for Globally Asynchronous Locally Synchronous Design, 2007

2006
Validating Families of Latency Insensitive Protocols.
IEEE Trans. Computers, 2006

A Trace Based Framework for Validation of SoC Designs with GALS Systems.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Polychronous Methodology For System Design: A True Concurrency Approach.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2005
XFM: An incremental methodology for developing formal models.
ACM Trans. Design Autom. Electr. Syst., 2005

A Functional Programming Framework for Latency Insensitive Protocol Validation.
Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design, 2005

System Level Design Methodology for System On Chips using Multi-Threaded Graphs.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

2004
A Formally Verified Application-Level Framework for Real-Time Scheduling on POSIX Real-Time Operating Systems.
IEEE Trans. Software Eng., 2004

Extreme Formal Modeling (XFM) for Hardware Models.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Effects of property ordering in an incremental formal modeling methodology.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004


  Loading...