Sriseshan Srikanth

Orcid: 0000-0001-9203-8011

According to our database1, Sriseshan Srikanth authored at least 16 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
SlimSLAM: An Adaptive Runtime for Visual-Inertial Simultaneous Localization and Mapping.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2022
Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems.
IEEE Trans. Computers, 2022

2021
SortCache: Intelligent Cache Management for Accelerating Sparse Data Workloads.
ACM Trans. Archit. Code Optim., 2021

2020
Energy efficient architectures for irregular data streams.
PhD thesis, 2020

MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams.
ACM Trans. Archit. Code Optim., 2020

Intrepydd: performance, productivity, and portability for data science application kernels.
Proceedings of the 2020 ACM SIGPLAN International Symposium on New Ideas, 2020

2019
Experimental Insights from the Rogues Gallery.
Proceedings of the 2019 IEEE International Conference on Rebooting Computing, 2019

2018
Extending Moore's Law via Computationally Error-Tolerant Computing.
ACM Trans. Archit. Code Optim., 2018

Tackling memory access latency through DRAM row management.
Proceedings of the International Symposium on Memory Systems, 2018

Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

2016
A Brief Survey of Non-Residue Based Computational Error Correction.
CoRR, 2016

Computationally-redundant energy-efficient processing for y'all (CREEPY).
Proceedings of the IEEE International Conference on Rebooting Computing, 2016

Energy efficiency limits of logic and memory.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016


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