Song Jia

Orcid: 0000-0002-4704-2510

According to our database1, Song Jia authored at least 44 papers between 2003 and 2024.

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Bibliography

2024
An eDRAM-Based Computing-in-Memory Macro With Full-Valid-Storage and Channel-Wise-Parallelism for Depthwise Neural Network.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024

2023
A label noise filtering and label missing supplement framework based on game theory.
Digit. Commun. Networks, August, 2023

A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS.
IEEE J. Solid State Circuits, 2023

2022
LEO Enhanced Global Navigation Satellite System (LeGNSS): progress, opportunities, and challenges.
Geo spatial Inf. Sci., 2022

A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Research on Intelligent Alarm Garbage Processing System Based on Internet of Things.
Proceedings of the 2022 International Conference on Artificial Intelligence, 2022

2021
Diversity-aware Web APIs Assignment and Recommendation for Mashup Creation with Compatibility Guarantee.
CoRR, 2021

2020
A Prediction Method for Soil Moisture Time Series.
Proceedings of the Machine Learning for Cyber Security - Third International Conference, 2020

2019
An algorithm for calculating coverage rate of WSNs based on geometry decomposition approach.
Peer-to-Peer Netw. Appl., 2019

Design of an Adaptive Loop Gain Controller Based on Auto-correlation Detection Scheme in All-Digital Phase-Locked Loop.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A Novel High-speed FPGA-based True Random Number Generator Based on Chaotic Ring Oscillator.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
A 1-Gbps reference-less burst-mode CDR with embedded TDC in a 65-nm CMOS process.
Int. J. Circuit Theory Appl., 2018

2017
Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process.
Int. J. Circuit Theory Appl., 2017

A reliable true random number generator based on novel chaotic ring oscillator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Design of a novel ternary SRAM sense amplifier using CNFET.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
A 4.8-6.8 GHz low phase noise LC VCO in 0.13-µm CMOS technology.
Int. J. Circuit Theory Appl., 2016

A true single-phase clock dual-modulus prescaler with enhanced robustness against leakage currents.
Int. J. Circuit Theory Appl., 2016

A Short-Time Three-Phase Single-Rail Precharge Logic against Differential Power Analysis.
IEICE Trans. Electron., 2016

Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process.
Sci. China Inf. Sci., 2016

Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Simplified carry save adder-based array multiplier scheme and circuits design.
Int. J. Circuit Theory Appl., 2015

Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling.
Sci. China Inf. Sci., 2015

180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A reference-less all-digital burst-mode CDR with embedded TDC.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A low power and high speed CAM design using pulsed voltage for search-line.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Design on multi-bit adder using sense amplifier-based pass transistor logic for near-threshold voltage operation.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A 10b, 0.7ps resolution coarse-fine time-to-digital converter in 65nm CMOS using a time residue amplifier.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013
Improved CRC Calculation Strategies for 64-bit Serial RapidIO.
IEICE Trans. Electron., 2013

A Current-Mirror Winner-Take-All Sense Amplifier for Low Voltage SRAMs.
IEICE Trans. Electron., 2013

Data Convertors Design for Optimization of the DDPL Family.
IEICE Trans. Electron., 2013

A current mode sense amplifier with self-compensation circuit for SRAM application.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A novel dynamic element match technique in current-steering DAC.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF).
IEICE Trans. Electron., 2012

Design of novel, semi-transparent flip-flops (STFF) for high speed and low power application.
Sci. China Inf. Sci., 2012

2011
Novel single-loop multi-bit sigma-delta modulator using OTA sharing technique without DEM.
IEICE Electron. Express, 2011

A novel multi-finger layout strategy for GGnMOS ESD protection device.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Low swing drivers based on charge redistribution.
Sci. China Inf. Sci., 2010

The Application of Three-Dimensional Visualization Technology in Village Information Service Platform.
Proceedings of the Computer and Computing Technologies in Agriculture IV, 2010

Study on the Rainfall Interpolation Algorithm of Distributed Hydrological Model Based on RS.
Proceedings of the Computer and Computing Technologies in Agriculture IV, 2010

2003
Design Retargetable Platform System for Microprocessor Functional Test.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003


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