Seng-Pan U
Affiliations:- University of Macau, China
According to our database1,
Seng-Pan U
authored at least 141 papers
between 1996 and 2021.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2016, "For leadership in the analog circuit design".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on fst.umac.mo
On csauthors.net:
Bibliography
2021
A 2.63 μW ECG Processor With Adaptive Arrhythmia Detection and Data Compression for Implantable Cardiac Monitoring Device.
IEEE Trans. Biomed. Circuits Syst., 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 2.52 μΑ Wearable Single Lead Ternary Neural Network Based Cardiac Arrhythmia Detection Processor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
A 17.7-pJ/Cycle ECG Processor for Arrhythmia Detection with High Immunity to Power Line Interference and Baseline Drift.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 550- $\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019
A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Quick and cost-efficient A/D converter static characterization using low-precision testing signal.
Microelectron. J., 2018
IEEE J. Solid State Circuits, 2018
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration.
IEEE J. Solid State Circuits, 2018
A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems.
Proceedings of the 2018 International Symposium on VLSI Design, 2018
A reconfigurable cross-connected wireless-power transceiver for bidirectional device-to-device charging with 78.1% total efficiency.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A Single-Stage Current-Mode Active Rectifier with Accurate Output-Current Regulation for IoT.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
A dual-output SC converter with dynamic power allocation for multicore application processors.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A 12b 180MS/s 0.068mm<sup>2</sup> With Full-Calibration-Integrated Pipelined-SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Microelectron. J., 2017
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration.
IEEE J. Solid State Circuits, 2017
20.5 A dual-symmetrical-output switched-capacitor converter with dynamic power cells and minimized cross regulation for application processors in 28nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
22.4 A reconfigurable bidirectional wireless power transceiver with maximum-current charging mode and 58.6% battery-to-battery efficiency.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
20.4 An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
F6: Pushing the performance limit in data converters organizers: Venkatesh Srinivasan, Texas Instruments, Dallas, TX.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 26th IEEE International Symposium on Industrial Electronics, 2017
CCM operation analysis and parameters design of Negative Output Elementary Luo Converter for ripple suppression.
Proceedings of the IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society, Beijing, China, October 29, 2017
A missing-code-detection gain error calibration achieving 63dB SNR for an 11-bit ADC.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS.
IEEE J. Solid State Circuits, 2016
Proceedings of the International Symposium on Integrated Circuits, 2016
A 12b 180MS/s 0.068mm<sup>2</sup> pipelined-SAR ADC with merged-residue DAC for noise reduction.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
A high DR multi-channel stage-shared hybrid front-end for integrated power electronics controller.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
A 0.011mm<sup>2</sup> 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Jitter-resistant Capacitor Based Sine-Shaped DAC for Continuous-Time Sigma-Delta modulators.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the ESSCIRC 2014, 2014
2013
IEEE J. Solid State Circuits, 2013
IEEE J. Solid State Circuits, 2013
A background gain- calibration technique for low voltage pipelined ADCs based on nonlinear interpolation.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation.
IEEE J. Solid State Circuits, 2012
IEEE J. Solid State Circuits, 2012
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
A 10MHz BW 78dB DR CT ΣΔ modulator with novel switched high linearity VCO-based quantizer.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique.
Proceedings of the 38th European Solid-State Circuit conference, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
A 0.024mm<sup>2</sup> 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the International SoC Design Conference, 2011
Proceedings of the 37th European Solid-State Circuits Conference, 2011
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
VLSI Design, 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
IEEE J. Solid State Circuits, 2010
1.2-V, 10-bit, 60-360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 μm CMOS with minimised supply headroom.
IET Circuits Devices Syst., 2010
A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2008
Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch.
IEEE Trans. Circuits Syst. II Express Briefs, 2008
On the Design of a Programmable-Gain Amplifier With Built-In Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
A process- and temperature- insensitive current-controlled delay generator for sampled-data systems.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
A novel CMOS switched-current mode sequential shift forward inference circuit for fuzzy logic controller.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
A pseudo-differential comparator-based pipelined ADC with common mode feedforward technique.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
Experimental 1-V flexible-IF CMOS analoguebaseband chain for IEEE 802.11a/b/g WLAN receivers.
IET Circuits Devices Syst., 2007
A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Design and test strategy underlying a low-voltage analog-baseband IC for 802.11a/b/g WLAN SiP receivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A novel effective bandpass semi-MASH sigma-delta modulator with double-sampling mismatch-free resonator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement Technique.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Two-step channel selection-a novel technique for reconfigurable multistandard transceiver front-ends.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A frequency up-conversion and two-step channel selection embedded CMOS D/A interface.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A robust 3rd order low-distortion multi-bit sigma-delta modulator with reduced number of op-amps for WCDMA.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A 1-V transient-free and DC-offset-canceled PGA with a 17.1-MHz constant bandwidth over 52-dB control range in 0.35-μm CMOS.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
Exact spectra analysis of sampled signals with jitter-induced nonuniformly holding effects.
IEEE Trans. Instrum. Meas., 2004
A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-μ hboxm CMOS.
IEEE J. Solid State Circuits, 2004
A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A 3D PWM control, H-bridge tri-level inverter for power quality compensation in three-phase four-wired systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A low-IF/zero-IF reconfigurable receiver with two-step channel selection technique for multistandard applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
An I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
A 10.7-MHz bandpass sigma-delta modulator using double-delay single-opamp SC resonator with double-sampling.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
A front-to-back-end modeling of I/Q mismatch effects in a complex-IF receiver for image-rejection enhancement.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Frequency-downconversion and IF channel selection A-DQS sample-and-hold pair for two-step-channel-select low-IF receiver.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003
A very area/power efficient mixed signal circuit for voice signal processing in 0.18 digital technology.
Proceedings of the ESSCIRC 2003, 2003
2002
Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
2001
A high-speed frequency up-translated SC bandpass filter with auto-zeroing for DDFS systems.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
High-frequency low-power multirate SC realizations for NTSC/PAL digital video filtering.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
A linear-phase halfband SC video interpolation filter with coefficient-sharing and spread-reduction.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
High performance multirate SC circuits with predictive correlated double sampling technique.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1998
A novel half-band SC architecture for efficient analog impulse sampled interpolation.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
1996
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996