Saranyu Chattopadhyay

Orcid: 0000-0002-4503-9297

According to our database1, Saranyu Chattopadhyay authored at least 11 papers between 2017 and 2023.

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Bibliography

2023
G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
LeGO: A Learning-Guided Obfuscation Framework for Hardware IP Protection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Proof-Stitch: Proof Combination for Divide and Conquer SAT Solvers.
CoRR, 2022

Proof-Stitch: Proof Combination for Divide-and-Conquer SAT Solvers.
Proceedings of the 22nd Formal Methods in Computer-Aided Design, 2022

2021
A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability.
ACM Trans. Design Autom. Electr. Syst., 2021

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition.
Proceedings of the Formal Methods in Computer Aided Design, 2021

2020
A-QED Verification of Hardware Accelerators.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Cyclic Beneš Network Based Logic Encryption for Mitigating SAT-Based Attacks.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Machine Learning Assisted Accurate Estimation of Usage Duration and Manufacturer for Recycled and Counterfeit Flash Memory Detection.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018
A novel technique for implementing reactance in spin domain using Spin Hall Effect.
Microelectron. J., 2018

2017
STT-MRAM for Low Power Access for Read-Intensive Parallel Deep-Learning Architectures.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017


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