Sanjay Das

Orcid: 0009-0005-4259-1915

According to our database1, Sanjay Das authored at least 8 papers between 1999 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
SCAR: Power Side-Channel Analysis at RTL Level.
IEEE Trans. Very Large Scale Integr. Syst., June, 2024

Analyzing and Mitigating Circuit Aging Effects in Deep Learning Accelerators.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

2023
Bottlenecks in Secure Adoption of Deep Neural Networks in Safety-Critical Applications.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Enhanced ML-Based Approach for Functional Safety Improvement in Automotive AMS Circuits.
Proceedings of the IEEE International Test Conference, 2023

Cryogenic In-memory Binary Multiplier Using Quantum Anomalous Hall Effect Memories.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Ternary In-Memory Computing with Cryogenic Quantum Anomalous Hall Effect Memories.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022
Adaptable Multi-level Voltage to Binary Converter Using Ferroelectric FETs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

1999
Key factors in road-rail mode choice in India: applying the logistics cost approach.
Proceedings of the 31st conference on Winter simulation: Simulation, 1999


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