Sanghyeon Baeg

Orcid: 0000-0002-6990-1312

According to our database1, Sanghyeon Baeg authored at least 39 papers between 1994 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Total-Ionizing Dose Damage from X-Ray PCB Inspection Systems.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

2023
Write Recovery Time Degradation by Thermal Neutrons in DDR4 DRAM Components.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

2021
Exploitations of Multiple Rows Hammering and Retention Time Interactions in DRAM Using X-Ray Radiation.
IEEE Access, 2021

DDR4 Data Channel Failure Due to DC Offset Caused by Intermittent Solder Ball Fracture in FBGA Package.
IEEE Access, 2021

Fault Coverage Re-Evaluation of Memory Test Algorithms With Physical Memory Characteristics.
IEEE Access, 2021

2019
Architectural design tradeoffs in SRAM-based TCAMs.
IEICE Electron. Express, 2019

2018
Study of proton radiation effect to row hammer fault in DDR4 SDRAMs.
Microelectron. Reliab., 2018

Failure signature analysis of power-opens in DDR3 SDRAMs.
Microelectron. Reliab., 2018

Signal characteristic and test exploitation for intermittent nanometer-scale cracks.
Microelectron. Reliab., 2018

Study of TID effects on one row hammering using gamma in DDR4 SDRAMs.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2017
Resource-Efficient SRAM-Based Ternary Content Addressable Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Temporal and frequency characteristic analysis of margin-related failures caused by an intermittent nano-scale fracture of the solder ball in a BGA package device.
Microelectron. Reliab., 2017

An alternative approach to measure alpha-particle-induced SEU cross-section for flip-chip packaged SRAM devices: High energy alpha backside irradiation.
Microelectron. Reliab., 2017

2016
Statistical distributions of row-hammering induced failures in DDR3 components.
Microelectron. Reliab., 2016

Experiments and root cause analysis for active-precharge hammering fault in DDR3 SDRAM under 3 × nm technology.
Microelectron. Reliab., 2016

Erratum: Assessing alpha-particle-induced SEU sensitivity of flip-chip bonded SRAM using high energy irradiation [IEICE Electronics Express Vol. 13 (2016) No. 17 pp. 20160627].
IEICE Electron. Express, 2016

Assessing alpha-particle-induced SEU sensitivity of flip-chip bonded SRAM using high energy irradiation.
IEICE Electron. Express, 2016

2015
Logic soft error study with 800-MHz DDR3 SDRAMs in 3x nm using proton and neutron beams.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory.
IEEE Trans. Computers, 2014

Single Event Resilient Dynamic Logic Designs.
J. Electron. Test., 2014

2013
Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication.
Microprocess. Microsystems, 2013

2012
Characterizing the Capacitive Crosstalk in SRAM Cells Using Negative Bit-Line Voltage Stress.
IEEE Trans. Instrum. Meas., 2012

Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Soft Error Issues with Scaling Technologies.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Mitigating the effects of large multiple cell upsets (MCUs) in memories.
ACM Trans. Design Autom. Electr. Syst., 2011

Design method of NOR-type comparison circuit in CAM with ground bounce noise considerations.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Designing ad-hoc scrubbing sequences to improve memory reliability against soft errors.
Proceedings of the 48th Design Automation Conference, 2011

2010
Minimizing Soft Errors in TCAM Devices: A Probabilistic Approach to Determining Scrubbing Intervals.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009
Null Detector Circuit Design Scheme for Detecting Defective AC-Coupled Capacitors in Differential Signaling.
IEEE Trans. Instrum. Meas., 2009

A di/dt Compensation Technique in Delay Testing by Disconnecting Power Pins.
IEEE Trans. Instrum. Meas., 2009

2008
Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Low Power Configuration Strategy of TCAM Lookup Table.
IEICE Trans. Commun., 2008

2007
Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006
Efficient Interconnect Test Patterns for Crosstalk and Static Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2005
Analytical test buffer design for differential signaling I/O buffers by error syndrome analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2005

2001
AC-JTAG: empowering JTAG beyond testing DC nets.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

1999
A cost-effective design for testability: clock line control and test generation using selective clocking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1994
Hybrid Design for Testability Combining Scan and Clock Line Control and Method for Test Generation.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994


  Loading...