Rui Bai

Affiliations:
  • PhotonIC Technologies Inc., Shanghai, China
  • Oregon State University, Corvallis, OR, USA (PhD 2014)


According to our database1, Rui Bai authored at least 20 papers between 2011 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2023
Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20-W/Ch Transmitter, and a 128 × 128 SPAD Receiver With SNR-Based Pixel Binning and Resolution Upscaling.
IEEE J. Solid State Circuits, March, 2023

dToF LIDAR System Using Addressable Multi-Channel VCSEL Transmitter, 128x80 SPAD Sensor, and ML-Based Object Detection for Adaptive Beam-Steering.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
An Integrated 200MHz 4A Pulsed Laser Driver with DLL-Based Time Interpolator for Indirect Time-of-Flight Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20W/Ch Transmitter, and a 128x128 SPAD Receiver with SNR-Based Pixel Binning and Resolution Upscaling.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021
A 4 × 10 Gb/s Adaptive Optical Receiver Utilizing Current-Reuse and Crosstalk-Remove.
IEEE Trans. Very Large Scale Integr. Syst., 2021

2020
PAM-X™: A 25Gb/s-PAM4 Optical Transceiver Chipset for 5G Optical Front-Haul.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020

2019
A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

2018
A 50Gb/s-PAM4 CDR with On-Chip Eye Opening Monitor for Reference-Level and Clock-Sampling Adaptation.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

A Fully-Integrated 25Gb/s Low-Noise TIA+CDR Optical Receiver designed in 40nm-CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization.
IEEE J. Solid State Circuits, 2016

2015
22.4 A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS.
IEEE J. Solid State Circuits, 2014

A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

2.5 A 0.25pJ/b 0.7V 16Gb/s 3-tap decision-feedback equalizer in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A 0.47-0.66 pJ/bit, 4.8-8 Gb/s I/O Transceiver in 65 nm CMOS.
IEEE J. Solid State Circuits, 2013

A ring-resonator-based silicon photonics transceiver with bias-based wavelength stabilization and adaptive-power-sensitivity receiver.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking.
IEEE J. Solid State Circuits, 2012

2011
Sinusoidal Clock Sampling for Multigigahertz ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011


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