Ritesh Bhat

Orcid: 0000-0001-9228-7245

According to our database1, Ritesh Bhat authored at least 8 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET.
IEEE J. Solid State Circuits, December, 2023

A 128Gb/s 1.95pJ/b D-Band Receiver with Integrated PLL and ADC in 22nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
A Fully Integrated 160-Gb/s D-Band Transmitter Achieving 1.1-pJ/b Efficiency in 22-nm FinFET.
IEEE J. Solid State Circuits, 2022

A Fully Integrated 160Gb/s D-Band Transmitter with 1.1 pJ/b Efficiency in 22nm FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Revolutionizing Aerospace and Defense: The Impact of AI and Robotics on Modern Warfare.
Proceedings of the 4th International Conference on Information Management & Machine Intelligence, 2022

2017
Wideband Mixed-Domain Multi-Tap Finite-Impulse Response Filtering of Out-of-Band Noise Floor in Watt-Class Digital Transmitters.
IEEE J. Solid State Circuits, 2017

13.10 A >1W 2.2GHz switched-capacitor digital power amplifier with wideband mixed-domain multi-tap FIR filtering of OOB noise floor.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
Design Tradeoffs and Predistortion of Digital Cartesian RF-Power-DAC Transmitters.
IEEE Trans. Circuits Syst. II Express Briefs, 2016


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