Ramesh Halli

According to our database1, Ramesh Halli authored at least 4 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A 3nm Ultra High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2.1 A 4nm 3.4GHz Tri-Gear Fully Out-of-Order ARMv9.2 CPU Subsystem-Based 5G Mobile SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
An Innovative Write Circuitry for Enhancing a 3nm L1 Cache Performance Across Wide DVFS Range.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2021
A 5nm Wide Voltage Range Ultra High Density SRAM Design for L2/L3 Cache Applications.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021


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