Priya Wali

Orcid: 0000-0002-1996-9319

According to our database1, Priya Wali authored at least 6 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2022
A Fractional-N Digital LC-PLL Using Coupled Frequency Doubler With Frequency-Tracking Loop for Wireline Applications.
IEEE J. Solid State Circuits, 2022

A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET.
IEEE J. Solid State Circuits, 2022

2021
A 56GHz Receiver Analog Front End for 224Gb/s PAM-4 SerDes in 10nm CMOS.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

11.5 A 23.9-to-29.4GHz Digital LC-PLL with a Coupled Frequency Doubler for Wireline Applications in 10nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021


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