Po-Chang Wu

According to our database, Po-Chang Wu authored at least 15 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2024

A 0.01-to-2.6-GHz Two-Fold Current Reuse Dual Noise-Canceling LNA Achieving 6.8-K Noise Temperature for Quantum Applications.

Mahesh Kumar Chaubey, Chih-Cheng Lin, Yin-Cheng Chang, Po-Chang Wu, Hann-Huei Tsai, Shawn S. H. Hsu

IEEE Trans. Circuits Syst. II Express Briefs, May, 2024

2020

A Low-Power Low-Noise Monolithic Accelerometer with Automatic Sensor Offset Calibration.

Chih-Yuan Yeh, Jung-Tang Huang, Sheng-Hsiang Tseng, Po-Chang Wu, Hann-Huei Tsai, Ying-Zong Juang

Microelectron. J., 2020

Late Breaking Results: Automatic Adaptive MOM Capacitor Cell Generation for Analog and Mixed-Signal Layout Design.

Tzu-Wei Wang, Po-Chang Wu, Mark Po-Hung Lin

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

A low-power monolithic three-axis accelerometer with automatically sensor offset compensated and interface circuit.

Chih-Yuan Yeh, Jung-Tang Huang, Sheng-Hsiang Tseng, Po-Chang Wu, Hann-Huei Tsai, Ying-Zong Juang

Microelectron. J., 2019

A Low-Cost 70Mbps Optical Detector Design For Optocoupler Application.

Yu-Chen Liu, Po-Chang Wu, Hann-Huei Tsai, Ying-Zong Juang

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

A 2.5D mm-size Wafer-level CMOS-IPD Wireless Power Transfer Receiver Using Cross-coupled and Self-biasing Topology for Implantable Biomedical System.

Kuei-Cheng Lin, Po-Chang Wu, Yu-Chen Liu, Hann-Huei Tsai, Ying-Zong Juang

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2017

An Efficient GPU-Based Multiple Pattern Matching Algorithm for Packet Filtering.

Che-Lun Hung, Chun-Yuan Lin, Po-Chang Wu

J. Signal Process. Syst., 2017

2016

Dielectric characterization and voltage holding ratio of blue-phase cells.

Po-Chang Wu, Hsuan-Tsung Hsu, Hsin-Li Chen, Wei Lee

Displays, 2016

A low power and low noise CMOS chopper amplifier for use in capacitive type accelerometer.

Chih-Yuan Yeh, Jung-Tang Huang, Po-Chang Wu, Hann-Huei Tsai, Ying-Zong Juang

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

Low-frequency noise reduction technique for accelerometer readout circuit.

Po-Chang Wu, Chih-Yuan Yeh, Hann-Huei Tsai, Ying-Zong Juang

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

Design of a 0.6-V 0.2-mW CMOS MEMS accelerometer.

Po-Chang Wu, Bin-Da Liu, Chih-Yuan Yeh, Sheng-Hsiang Tseng, Hann-Huei Tsai, Ying-Zong Juang

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2015

Efficient Parallel Muti-pattern Matching Using GPGPU Acceleration for Packet Filtering.

Che-Lun Hung, Po-Chang Wu, Hsiao-Hsi Wang, Chun-Yuan Lin

Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

2014

5-GHz SiGe linearity power amplifier using integrated feedforward architecture for WLAN applications.

Kuei-Cheng Lin, Hwann-Kaeo Chiou, Po-Chang Wu, Hann-Huei Tsai, Ying-Zong Juang

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Novel automatic offset cancellation approach for capacitive CMOS MEMS accelerometers.

Po-Chang Wu, Bin-Da Liu, Yu-Chen Teng, Chih-Yuan Yeh, Sheng-Hsiang Tseng, Hann-Huei Tsai, Ying-Zong Juang

Proceedings of the IEEE International Symposium on Consumer Electronics, 2013

2012

Variable gain active predistorter with linearity enhancement for a 2.4 GHz SiGe HBT power amplifier design.

Kuei-Cheng Lin, Hwann-Kaeo Chiou, Po-Chang Wu, Chu-Jung Sha, Chun-Lin Ko, Da-Chiang Chang, Ying-Zong Juang

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012