Philip G. Emma

According to our database1, Philip G. Emma authored at least 44 papers between 1987 and 2018.

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Bibliography

2018
Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts Via Data Duplication.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

2014
3D stacking of high-performance processors.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2009
Opportunities and Challenges for 3D Systems and Their Design.
IEEE Des. Test Comput., 2009

2008
Rethinking Refresh: Increasing Availability and Reducing Power in DRAM for Cache Applications.
IEEE Micro, 2008

Guest Editor's Introduction: Existential Architectures: The Metaphysics of Computer Design.
IEEE Micro, 2008

A Collaborative IP-Development Session.
IEEE Micro, 2008

Analyzing the Cost of a Cache Miss Using Pipeline Spectroscopy.
J. Instr. Level Parallelism, 2008

On the Nature of Cache Miss Behavior: Is It √2?
J. Instr. Level Parallelism, 2008

Is 3D chip technology the next growth engine for performance improvement?
IBM J. Res. Dev., 2008

2007
You're Invited to a Party! (How To Hold a Collaborative IP-Development Session).
IEEE Micro, 2007

Supercharging Your Creative Skills.
IEEE Micro, 2007

Innovation or Notoriety?
IEEE Micro, 2007

Arcane Facts and New Words: Expanding Your Creative Talent.
IEEE Micro, 2007

Reinventing Entrepreneurial Inventing for the 21st Century.
IEEE Micro, 2007

Pipeline spectroscopy.
Proceedings of the 2007 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2007

Interconnects in the Third Dimension: Design Challenges for 3D ICs.
Proceedings of the 44th Design Automation Conference, 2007

An analysis of the effects of miss clustering on the cost of a cache miss.
Proceedings of the 4th Conference on Computing Frontiers, 2007

2006
Five strategies for overcoming obviousness.
IEEE Micro, 2006

Prosecuting your patent.
IEEE Micro, 2006

The Mechanics of Filing a Patent.
IEEE Micro, 2006

Patent Claims Revisited: Examiners and Trolls.
IEEE Micro, 2006

The best patents of all.
IEEE Micro, 2006

How to write a patent.
IEEE Micro, 2006

The End of Scaling? Revolutions in Technology and Microarchitecture as We Pass the 90 Nanometer Node.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

Industrial Perspectives: The Next Roadblocks in SOC Evolution: On-Chip Storage Capacity and Off-Chip Bandwidth.
Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

Cache miss behavior: is it sqrt(2)?
Proceedings of the Third Conference on Computing Frontiers, 2006

2005
Writing the claims for a patent.
IEEE Micro, 2005

Patents: To file or not to file?
IEEE Micro, 2005

What is patentable?
IEEE Micro, 2005

Inventions and the creative process.
IEEE Micro, 2005

Exploring the limits of prefetching.
IBM J. Res. Dev., 2005

When prefetching improves/degrades performance.
Proceedings of the Second Conference on Computing Frontiers, 2005

2004
Integrated Analysis of Power and Performance for Pipelined Microprocessors.
IEEE Trans. Computers, 2004

2003
New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors.
IBM J. Res. Dev., 2003

2002
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002

Optimizing pipelines for power and performance.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

1997
Improving the Accuracy of History Based Branch Prediction.
IEEE Trans. Computers, 1997

A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders.
IEEE J. Solid State Circuits, 1997

Understanding some simple processor-performance limits.
IBM J. Res. Dev., 1997

1996
Computer architecture education in a corporate reengineering program.
Proceedings of the 1996 workshop on Computer architecture education, 1996

1992
Contrasting instruction-fetch time and instruction-decode time branch prediction mechanisms: Achieving synergy through their cooperative operation.
Microprocess. Microprogramming, 1992

1991
Branch History Table Prediction of Moving Target Branches due to Subroutine Returns.
Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991

1989
Simulation and analysis of a pipeline processor.
Proceedings of the 21st Winter Simulation Conference, 1989

1987
Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance.
IEEE Trans. Computers, 1987


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