Peter Hailes

According to our database, Peter Hailes authored at least 5 papers between 2016 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations.

Shuai Shao, Peter Hailes, Tsang-Yi Wang, Jwo-Yuh Wu, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo

IEEE Commun. Surv. Tutorials, 2019

2018

Hardware-Efficient Node Processing Unit Architectures for Flexible LDPC Decoder Implementations.

Peter Hailes, Lei Xu, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo

IEEE Trans. Circuits Syst. II Express Briefs, 2018

2017

A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder.

Peter Hailes, Lei Xu, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo

IEEE Access, 2017

2016

A Survey of FPGA-Based LDPC Decoders.

Peter Hailes, Lei Xu, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo

IEEE Commun. Surv. Tutorials, 2016

1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications.

An Li, Peter Hailes, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo

IEEE Access, 2016