Na Bai

Orcid: 0000-0003-2396-5991

According to our database1, Na Bai authored at least 17 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
A 14T radiation hardened SRAM for space applications with high reliability.
Int. J. Circuit Theory Appl., June, 2024

Soft-Error-Aware SRAM With Multinode Upset Tolerance for Aerospace Applications.
IEEE Trans. Very Large Scale Integr. Syst., January, 2024

Deep Learning Methods With the Improved Attention for Explainable Image Recognition.
IEEE Access, 2024

2023
Design of SEU and DNU-resistant SRAM cells based on polarity reinforcement feature.
Int. J. Circuit Theory Appl., October, 2023

A multi-task attention tree neural net for stance classification and rumor veracity detection.
Appl. Intell., May, 2023

JUTAR: Joint User-Association, Task-Partition, and Resource-Allocation Algorithm for MEC Networks.
Sensors, February, 2023

Highly stable soft-error immune SRAM with multi-node upset recovery for aerospace applications.
Integr., 2023

2022
An interpretable deep learning workflow for discovering subvisual abnormalities in CT scans of COVID-19 inpatients and survivors.
Nat. Mach. Intell., 2022

Naive Bayes classifier based on memristor nonlinear conductance.
Microelectron. J., 2022

Rumor detection based on a Source-Replies conversation Tree Convolutional Neural Net.
Computing, 2022

Logic Design and Power Optimization of Floating-Point Multipliers.
Comput. Intell. Neurosci., 2022

2021
A Design of a Developable Automatic Avoidance System of UAV Based on ADS-B.
Wirel. Commun. Mob. Comput., 2021

Rumour Detection Based on Graph Convolutional Neural Net.
IEEE Access, 2021

2020
A Stochastic Attention CNN Model for Rumor Stance Classification.
IEEE Access, 2020

2014
A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for Reducing Timing Variation of SRAM Sense Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

2013
A low active and leakage power SRAM using a read and write divided and BIST programmable timing control circuit.
Microelectron. J., 2013

2012
Bitline Leakage Current Compensation Circuit for High-Performance SRAM Design.
Proceedings of the Seventh IEEE International Conference on Networking, 2012


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