Moyang Wang

Orcid: 0009-0009-4951-3468

According to our database1, Moyang Wang authored at least 12 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2024
Position-Aware Graph-CNN Fusion Network: An Integrated Approach Combining Geospatial Information and Graph Attention Network for Multiclass Change Detection.
IEEE Trans. Geosci. Remote. Sens., 2024

Change detection on multi-sensor imagery using mixed interleaved group convolutional network.
Eng. Appl. Artif. Intell., 2024

A Survey on Applications of Reinforcement Learning in Spatial Resource Allocation.
CoRR, 2024

2023
Optimizing pedestrian simulation based on expert trajectory guidance and deep reinforcement learning.
GeoInformatica, October, 2023

Transform paper-based cadastral data into digital systems using GIS and end-to-end deep learning techniques.
Int. J. Geogr. Inf. Sci., 2023

CIFER: A 12nm, 16mm<sup>2</sup>, 22-Core SoC with a 1541 LUT6/mm<sup>2</sup> 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
Assessing Street Space Quality Using Street View Imagery and Function-Driven Method: The Case of Xiamen, China.
ISPRS Int. J. Geo Inf., 2022

2020
A Deep Siamese Network with Hybrid Convolutional Feature Extraction Module for Change Detection Based on Multi-sensor Remote Sensing Images.
Remote. Sens., 2020

Efficiently Supporting Dynamic Task Parallelism on Heterogeneous Cache-Coherent Systems.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2017
Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

2016
Asymmetry-Aware Work-Stealing Runtimes.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Experiences using a novel Python-based hardware modeling framework for computer architecture test chips.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016


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