Motokazu Ozawa

According to our database, Motokazu Ozawa authored at least 8 papers between 1997 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2006

Development of processor cores for digital consumer appliances.

Fumio Arakawa, Tetsuya Yamada, Takashi Okada, Makoto Ishikawa, Yuki Kondo, Motokazu Ozawa, Tomoyuki Kodama, Osamu Nishii, Toshihiro Hattori, Tatsuya Kamei, Junichi Nishimoto, Shinichi Yoshioka

Syst. Comput. Jpn., 2006

Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core.

Tetsuya Yamada, Masahide Abe, Yusuke Nitta, Kenji Ogura, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Takada, Fumio Arakawa, Osamu Nishii, Toshihiro Hattori

IEICE Trans. Electron., 2006

2005

SH-X: an embedded processor core for consumer appliances.

Fumio Arakawa, Makoto Ishikawa, Yuki Kondo, Tatsuya Kamei, Motokazu Ozawa, Osamu Nishii, Toshihiro Hattori

SIGARCH Comput. Archit. News, 2005

A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones.

Makoto Ishikawa, Tatsuya Kamei, Yuki Kondo, Masanao Yamaoka, Yasuhisa Shimazaki, Motokazu Ozawa, Saneaki Tamaki, Mikio Furuyama, Tadashi Hoshi, Fumio Arakawa, Osamu Nishii, Kenji Hirose, Shinichi Yoshioka, Toshihiro Hattori

IEICE Trans. Electron., 2005

Low-Power Design of 90-nm SuperH Processor Core.

Tetsuya Yamada, Masahide Abe, Yusuke Nitta, Kenji Ogura, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Takada, Fumio Arakawa, Osamu Nishii, Toshihiro Hattori

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2001

Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors.

Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno

Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001

1998

TITAC-2: An Asynchronous 32-bit Microprocessor.

Akihiro Takamura, Motokazu Ozawa, Izumi Fukasaku, Taro Fujii, Yoichiro Ueno, Masashi Imai, Masashi Kuwako, Takashi Nanya

Proceedings of the ASP-DAC '98, 1998

1997

TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model.

Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997