Mochamad Asri

According to our database, Mochamad Asri authored at least 11 papers between 2011 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

CASPHAr: Cache-Managed Accelerator Staging and Pipelining in Heterogeneous System Architectures.

Mochamad Asri, Andreas Gerstlauer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021

Hardware Accelerator Integration Tradeoffs for High-Performance Computing: A Case Study of GEMM Acceleration in N-Body Methods.

Mochamad Asri, Dhairya Malhotra, Jiajun Wang, George Biros, Lizy K. John, Andreas Gerstlauer

IEEE Trans. Parallel Distributed Syst., 2021

2020

The Non-Uniform Compute Device (NUCD) Architecture for Lightweight Accelerator Offload.

Mochamad Asri, Curtis Dunham, Roxana Rusitoru, Andreas Gerstlauer, Jonathan Beard

Proceedings of the 28th Euromicro International Conference on Parallel, 2020

2016

Simulator calibration for accelerator-rich architecture studies.

Mochamad Asri, Ardavan Pedram, Lizy K. John, Andreas Gerstlauer

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

2013

Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing.

Hsuanchun Liao, Mochamad Asri, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

J. Inf. Process., 2013

A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine.

Hsuanchun Liao, Mochamad Asri, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

2012

A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing.

Hsuanchun Liao, Mochamad Asri, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

A Reconfigurable High Performance ASIP Engine for Image Signal Processing.

Hsuanchun Liao, Mochamad Asri, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

A reconfigurable ASIP-based approach for high performance image signal processing.

Mochamad Asri, Hsuanchun Liao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

Rethinking processor instruction fetch: Inefficiencies-cracking mechanism.

Mochamad Asri, Naoki Fujieda, Kenji Kise

Proceedings of the International SoC Design Conference, 2011

Efficient fetch mechanism by employing instruction register.

Mochamad Asri

Proceedings of the 2011 IEEE Hot Chips 23 Symposium (HCS), 2011