Mitsuyuki Ashida

Orcid: 0000-0002-4399-4135

According to our database1, Mitsuyuki Ashida authored at least 6 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A Mueller-Müller CDR with False-Lock-Aware Locking Scheme for a 56-Gb/s ADC-Based PAM4 Transceiver.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024

2022
A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems.
IEEE J. Solid State Circuits, 2022

A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2019
A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018

2004
A +10-dBm IIP<sub>3</sub> SiGe mixer with IM<sub>3</sub> cancellation technique.
IEEE J. Solid State Circuits, 2004


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