Max M. Shulaker

Orcid: 0000-0003-2237-193X

According to our database1, Max M. Shulaker authored at least 25 papers between 2011 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Foundry Monolithic 3D BEOL Transistor + Memory Stack: Iso-performance and Iso-footprint BEOL Carbon Nanotube FET+RRAM vs. FEOL Silicon FET+RRAM.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2020
Advances in Carbon Nanotube Technologies: From Transistors to a RISC-V Microprocessor.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

2019
The N3XT Approach to Energy-Efficient Abundant-Data Computing.
Proc. IEEE, 2019

Monolithic 3-D Integration.
IEEE Micro, 2019

Special Session (New Topic): Emerging Computing and Testing Techniques.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

SHARC: Self-Healing Analog with RRAM and CNFETs.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration.
IEEE J. Solid State Circuits, 2018

Hyperdimensional Computing Nanosystem.
CoRR, 2018

Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs.
Proceedings of the 55th Annual Design Automation Conference, 2018

2016
Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Keynote address: Challenges and opportunities in electrical characterization and test for 14nm and below.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Transforming nanodevices to next generation nanosystems.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

2015
Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Energy-Efficient Abundant-Data Computing: The N3XT 1, 000x.
Computer, 2015

Time-based sensor interface circuits in carbon nanotube technology.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Monolithic 3D integration: a path from concept to reality.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs.
IEEE J. Solid State Circuits, 2014

Robust design and experimental demonstrations of carbon nanotube digital circuits.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Carbon nanotube circuits: opportunities and challenges.
Proceedings of the Design, Automation and Test in Europe, 2013

Sacha: the Stanford carbon nanotube controlled handshaking robot.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Rapid exploration of processing and design guidelines to overcome carbon nanotube variations.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2011
Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011


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