Linxiao Shen

Orcid: 0000-0001-7933-3673

According to our database1, Linxiao Shen authored at least 52 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A 0.39-mm<sup>2</sup> Stacked Standard-CMOS Humidity Sensor Using a Charge-Redistribution Correlated Level Shifting Floating Inverter Amplifier and a VCO-Based Zoom CDC.
IEEE J. Solid State Circuits, February, 2024

9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
Research progress on low-power artificial intelligence of things (AIoT) chip design.
Sci. China Inf. Sci., October, 2023

Interactive Analog Layout Editing With Instant Placement and Routing Legalization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023

An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023

A Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023

Post-Layout Simulation Driven Analog Circuit Sizing.
CoRR, 2023

A 0.954nW 32kHz Crystal Oscillator in 22nm CMOS with Gm-C-Based Current Injection Control.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

An Information-Aware Adaptive Data Acquisition System using Level-Crossing ADC with Signal-Dependent Full Scale and Adaptive Resolution for IoT Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022
Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 32-ppm/°C 0.9-nW/kHz Relaxation Oscillator with Event-Driven Architecture and Charge Reuse Technique.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation Scheme.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021
The Challenges and Emerging Technologies for Low-Power Artificial Intelligence IoT Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Software-Defined Always-On System With 57-75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC.
IEEE J. Solid State Circuits, 2021

A 148-nW Reconfigurable Event-Driven Intelligent Wake-Up System for AIoT Nodes Using an Asynchronous Pulse-Based Feature Extractor and a Convolutional Neural Network.
IEEE J. Solid State Circuits, 2021

A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS.
IEEE J. Solid State Circuits, 2021

Energy-Efficient CMOS Humidity Sensors Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array.
IEEE J. Solid State Circuits, 2021

10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SAR.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS.
IEEE J. Solid State Circuits, 2020

A 0.025-mm<sup>2</sup> 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure.
IEEE J. Solid State Circuits, 2020

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier.
IEEE J. Solid State Circuits, 2020

An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier.
IEEE J. Solid State Circuits, 2020

An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter.
IEEE J. Solid State Circuits, 2020

A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique.
IEEE J. Solid State Circuits, 2020

A 13-bit 0.005-mm<sup>2</sup> 40-MS/s SAR ADC With kT/C Noise Cancellation.
IEEE J. Solid State Circuits, 2020

A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

16.5 A 13b 0.005mm<sup>2</sup> 40MS/s SAR ADC with kT/C Noise Cancellation.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

A Power-Efficient 13-Tap FIR filter and an IIR Filter Embedded in a 10-bit SAR ADC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

S<sup>3</sup>DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
A Two-Step ADC With a Continuous-Time SAR-Based First Stage.
IEEE J. Solid State Circuits, 2019

An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 0.01mm<sup>2</sup> 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Device Layer-Aware Analytical Placement for Analog Circuits.
Proceedings of the 2019 International Symposium on Physical Design, 2019

WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 0.025-mm<sup>2</sup> 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A 1-V 0.25-µW Inverter Stacking Amplifier With 1.07 Noise Efficiency Factor.
IEEE J. Solid State Circuits, 2018

A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
NFC-enabled, tattoo-like stretchable biosensor manufactured by "cut-and-paste" method.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017


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