Kumiko Nomura

According to our database1, Kumiko Nomura authored at least 20 papers between 2001 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Synchronized Stepwise Control of Firing and Learning Thresholds in a Spiking Randomly Connected Neural Network toward Hardware Implementation.
CoRR, 2024

2020
Dynamic Firing on Static Analog/Digital Neuron Circuits with Resistive Synapses for Time-Series Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Nonlinear Operation of Static-Binary Neuron Circuits and Dynamic Memristive Devices for STDP Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Novel memory hierarchy with e-STT-MRAM for near-future applications.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2014
Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Novel nonvolatile memory hierarchies to realize "normally-off mobile processors".
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2010
Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
On the two-dimensional orthogonal drawing of series-parallel graphs.
Discret. Appl. Math., 2009

Perspectives and Issues in 3D-IC from Designers' Point of View.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
On the three-dimensional orthogonal drawing of series-parallel graphs (extended abstract).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

2006
Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

3D on-chip networking technology based on post-silicon devices for future networks-on-chip.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

2005
On the Orthogonal Drawing of Outerplanar Graphs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

2004
Sparse networks tolerating random faults.
Discret. Appl. Math., 2004

2003
Optimal adaptive parallel diagnosis for arrays.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2001
On Adaptive Fault Diagnosis for Multiprocessor Systems.
Proceedings of the Algorithms and Computation, 12th International Symposium, 2001


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