Kui Dai

According to our database1, Kui Dai authored at least 73 papers between 2004 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
ARCE: Towards Code Pointer Integrity on Embedded Processors Using Architecture-Assisted Run-Time Metadata Management.
IEEE Comput. Archit. Lett., 2019

2018
A Reliable Strong PUF Based on Switched-Capacitor Circuit.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor.
IEICE Trans. Inf. Syst., 2018

2016
A Novel Thyristor-Based Silicon Physical Unclonable Function.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Nonlinearity-Compensated All-MOS Voltage-to-Current Converter.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

BFWindow: Speculatively Checking Data Property Consistency against Buffer Overflow Attacks.
IEICE Trans. Inf. Syst., 2016

2015
An Invasive-Attack-Resistant PUF Based On Switched-Capacitor Circuit.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 2/3 Dual-Modulus Prescaler Using Complementary Clocking NMOS-Like Blocks.
J. Circuits Syst. Comput., 2015

A 1-V 2.5-ppm/°C second-order compensated bandgap reference.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Mac or Non-MAC: not a Problem.
J. Circuits Syst. Comput., 2014

A Compact Hardware Implementation of SM3 Hash Function.
Proceedings of the 13th IEEE International Conference on Trust, 2014

2011
Implementation and evaluation of parallel FFT on Engineering and Scientific Computation Accelerator (ESCA) architecture.
J. Zhejiang Univ. Sci. C, 2011

An area-efficient 5GHz/10GHz dual-mode VCO with coupled helical inductors in 0.13-UM CMOS technology.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

2010
New design of RF rectifier for passive UHF RFID transponders.
Microelectron. J., 2010

A High Efficient On-Chip Interconnection Network in SIMD CMPs.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2010

The parallel algorithm implementation of matrix multiplication based on ESCA.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Implementation of OpenVG Path and Paint Algorithms on Synchronous Data Triggered Architecture with Optimization.
Proceedings of the International Conference on Networking, Architecture, and Storage, 2009

2008
A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique.
J. Electron. Test., 2008

Control flow checking and recovering based on 8051 architecture.
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

Hierarchical memory system design for a heterogeneous multi-core processor.
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

Transient Fault Tolerance on Chip Multiprocessor Based on Dual and Triple Core Redundancy.
Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008

A New CORDIC Algorithm and Software Implementation Based on Synchronized Data Triggering Architecture.
Proceedings of the 2008 International Conference on Multimedia and Ubiquitous Engineering (MUE 2008), 2008

Performance Bound Analysis and Retiming of Timed Circuits.
Proceedings of the 9th International Conference for Young Computer Scientists, 2008

The P2P Communication Model for a Local Memory based Multi-core Processor.
Proceedings of the 9th International Conference for Young Computer Scientists, 2008

Transient Fault Recovery on Chip Multiprocessor based on Dual Core Redundancy and Context Saving.
Proceedings of the 9th International Conference for Young Computer Scientists, 2008

Low-Level Component for OpenGL ES Oriented Heterogeneous Architecture with Optimization.
Proceedings of the 9th International Conference for Young Computer Scientists, 2008

A Framework to Evaluate the Trade-off among AVF Performance and Area of Soft Error Tolerant Microprocessors.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers.
Proceedings of the 45th Design Automation Conference, 2008

Memory System Design for a Multi-core Processor.
Proceedings of the Second International Conference on Complex, 2008

2007
Design and Test of Self-checking Asynchronous Control Circuit.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Template Vertical Dictionary-Based Program Compression Scheme on the TTA.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Hardware Support for Arithmetic Units of Processor with Multimedia Extension.
Proceedings of the 2007 International Conference on Multimedia and Ubiquitous Engineering (MUE 2007), 2007

The Research of an Embedded Processor Element for Multimedia Domain.
Proceedings of the Multimedia Content Analysis and Mining, International Workshop, 2007

Security Event Management System based on Mobile Agent Technology.
Proceedings of the IEEE International Conference on Intelligence and Security Informatics, 2007

Latency Estimation of the Asynchronous Pipeline Using the Max-Plus Algebra.
Proceedings of the Computational Science - ICCS 2007, 7th International Conference, Beijing, China, May 27, 2007

A Low-Power Globally Synchronous Locally Asynchronous FFT Processor.
Proceedings of the High Performance Computing and Communications, 2007

A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design.
Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 2007

An Optimal Design Method for De-synchronous Circuit Based on Control Graph.
Proceedings of the Advanced Parallel Processing Technologies, 7th International Symposium, 2007

Design of a Low-Power Embedded Processor Architecture Using Asynchronous Function Units.
Proceedings of the Advances in Computer Systems Architecture, 2007

A Low-Power Application Specific Instruction Set Processor Using Asynchronous Function Units.
Proceedings of the Seventh International Conference on Computer and Information Technology (CIT 2007), 2007

2006
Research and Implementation of a 32-Bit Asynchronous Multiplier.
J. Comput. Res. Dev., 2006

A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology.
Proceedings of the IFIP VLSI-SoC 2006, 2006

An Efficient Way to Build Secure Disk.
Proceedings of the Information Security Practice and Experience, 2006

A PCA-LVQ Model for Intrusion Alert Analysis.
Proceedings of the Intelligence and Security Informatics, 2006

Intrusion Alert Analysis Based on PCA and the LVQ Neural Network.
Proceedings of the Neural Information Processing, 13th International Conference, 2006

A Novel Data-Parallel Coprocessor for Multimedia Signal Processing.
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006

A Heterogeneous Embedded MPSoC for Multimedia Applications.
Proceedings of the High Performance Computing and Communications, 2006

A High Performance Heterogeneous Architecture and Its Optimization Design.
Proceedings of the High Performance Computing and Communications, 2006

Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

A Dual-core Embedded System-on-Chip Architecture for Multimedia Signal Processing Applications.
Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006

Improving the Fault Tolerance of a Computer System with Space-Time Triple Modular Redundancy.
Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006

Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor Using WDDL and Wave-Pipelining.
Proceedings of the Information Security and Cryptology, Second SKLOIS Conference, 2006

Cycle Period Analysis and Optimization of Timed Circuits.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

A Heterogeneous Multi-core Processor Architecture for High Performance Computing.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

An Approximate Method for Performance Evaluation of Asynchronous Pipeline Rings.
Proceedings of the Sixth International Conference on Computer and Information Technology (CIT 2006), 2006

Two New Space-Time Triple Modular Redundancy Techniques for Improving Fault Tolerance of Computer Systems.
Proceedings of the Sixth International Conference on Computer and Information Technology (CIT 2006), 2006

2005
Design and Implementation a TPM Chip SUP320 by SOC.
Proceedings of the Security and Privacy in the Age of Ubiquitous Computing, IFIP TC11 20th International Conference on Information Security (SEC 2005), May 30, 2005

Research on Risk Probability Estimating Using Fuzzy Clustering for Dynamic Security Assessment.
Proceedings of the Rough Sets, 2005

Trust-Enhanced Alteration Scenario for Universal Computer.
Proceedings of the 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 2005

Protecting Mass Data Basing on Small Trusted Agent.
Proceedings of the Information Security Practice and Experience, 2005

Design of a Configurable Embedded Processor Architecture for DSP Functions.
Proceedings of the 11th International Conference on Parallel and Distributed Systems, 2005

Research on Fuzzy Group Decision Making in Security Risk Assessment.
Proceedings of the Networking, 2005

A Fast Motion Estimation Algorithm Based on Diamond and Triangle Search Patterns.
Proceedings of the Pattern Recognition and Image Analysis, Second Iberian Conference, 2005

Retargetable Machine-Description System: Multi-layer Architecture Approach.
Proceedings of the Grid and Cooperative Computing - GCC 2005, 4th International Conference, Beijing, China, November 30, 2005

Research on intra modes for inter-frame coding in H.264.
Proceedings of the Ninth International Conference on Computer Supported Cooperative Work in Design, 2005

A Fast Motion Estimation Algorithm Based on Diamond and Simplified Square Search Patterns.
Proceedings of the Progress in Pattern Recognition, 2005

Research on Fast Block Participation Mode Selection Algorithm in H.264.
Proceedings of the 4th Annual ACIS International Conference on Computer and Information Science (ICIS 2005), 2005

2004
A network intrusion detection system based on the artificial neural networks.
Proceedings of the 3rd International Conference on Information Security, 2004

Applying multiple criteria decision making to improve security architecture development.
Proceedings of the 3rd International Conference on Information Security, 2004

A New Technique for Program Code Compression in Embedded Microprocessor.
Proceedings of the Embedded Software and Systems, First International Conference, 2004

Analysis of Inter-Frame Coding Without Intra Modes in H.264.
Proceedings of the 7th Eurographics Multimedia Workshop 2004, 2004

Improving Security Architecture Development Based on Multiple Criteria Decision Making.
Proceedings of the Content Computing, Advanced Workshop on Content Computing, 2004

TengYue-1TengYue: In Chinese means jump over.: A High Performance Embedded SoC.
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004


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