K. Wayne Current

According to our database, K. Wayne Current authored at least 39 papers between 1978 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2008

Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits.

Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

2007

A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System.

K. Wayne Current, Kelvin Yuk, Charles McConaghy, Peter R. C. Gascoyne, Jon A. Schwartz, Jody V. Vykoukal, Craig Andrews

IEEE Trans. Biomed. Circuits Syst., 2007

2005

A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers.

Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija

Proceedings of the Integrated Circuit and System Design, 2005

A High-Voltage Integrated Circuit Engine for a Dielectrophoresis-based Programmable Micro-Fluidic Processor.

K. Wayne Current, Kelvin Yuk, Charles McConaghy, Peter R. C. Gascoyne, Jon A. Schwartz, Jody V. Vykoukal, Craig Andrews

Proceedings of the 2005 International Conference on MEMS, 2005

2004

Low-Power Voltage Comparator Circuit for CMOS Quaternary Logic.

Yongjian Brandon Guo, K. Wayne Current

J. Multiple Valued Log. Soft Comput., 2004

2002

Voltage Comparator Circuits for Multiple-Valued CMOS Logic.

Yongjian Brandon Guo, K. Wayne Current

Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

2000

Clocked CMOS adiabatic logic with integrated single-phase power-clock supply.

Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current

IEEE Trans. Very Large Scale Integr. Syst., 2000

Partitioned Branch Condition Resolution Logic.

Aamir A. Farooqui, K. Wayne Current, Vojin G. Oklobdzija

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Hardware Implementation of "Supplementary Symmetrical Logic Circuit Structure" Concepts.

Dan Olson, K. Wayne Current

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch.

K. Wayne Current

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

1998

CMOS implementation of low-power oscillators based on the modified Fabre-Normand current conveyor.

Jelena Popovic, Borivoje Nikolic, K. Wayne Current, Aleksandra Pavasovic, Dragan Vasiljevic

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1997

Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results.

Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

1996

Low-Energy Logic Circuit Techniques for Multiple-Valued Logic.

K. Wayne Current, Vojin G. Oklobdzija, Dragan Maksimovic

Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

1995

A CMOS continuous-time NTSC-to-color-difference decoder.

James F. Parker, K. Wayne Current, Stephen H. Lewis

IEEE J. Solid State Circuits, December, 1995

Memory Circuits for Multiple-Valued Logic Voltage Signals.

K. Wayne Current

Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

1994

Current-mode CMOS multiple-valued logic circuits.

K. Wayne Current

IEEE J. Solid State Circuits, February, 1994

Quaternary Multiplier Circuit.

Wei-Shang Chu, K. Wayne Current

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

1993

Multiple Valued Logic: Current-Mode CMOS Circuits.

K. Wayne Current

Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993

Block-Diagram-Level Design Capture, Functional Simulation, and Layout Assembly of Analog CMOS ICs.

K. Wayne Current, James F. Parker, Wes Hardaker

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992

High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture.

Eric Shieh, K. Wayne Current, Paul J. Hurst, Iskender Agi

IEEE Trans. Circuits Syst. Video Technol., 1992

A Current-Mode CMOS Algorithmic Analog-to-Quaternary Converter Circuit.

K. Wayne Current

Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992

1991

A Bi-Directional Current-Mode CMOS Multiple-Valued Logic Memory Circuit.

K. Wayne Current, M. E. Hurlston

Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991

A new VLSI architecture for real-time control of robot manipulators.

J. Liu, Ziqiang Mao, G. Z. Lu, W. H. Han, Tien C. Hsia, K. Wayne Current, Wei-Shang Chu

Proceedings of the 1991 IEEE International Conference on Robotics and Automation, 1991

1990

An evaluation of Radon transform computations using DSP chips.

K. Wayne Current, Paul J. Hurst, Eric Shieh, Iskender Agi

Mach. Vis. Appl., 1990

A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent Latch.

K. Wayne Current

Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990

A VLSI architecture for two-dimensional Radon transform computations.

Paul J. Hurst, K. Wayne Current, Iskender Agi, Eric Shieh

Proceedings of the 1990 International Conference on Acoustics, 1990

1989

An architecture for region boundary extraction in raster scan images suitable for VLSI implementation.

James M. Apffel, K. Wayne Current, Jorge L. C. Sanz, Anil K. Jain

Mach. Vis. Appl., 1989

A Radon transform computer for multidimensional signal processing.

Stephen G. Azevedo, James M. Brase, Harry E. Martz, Anil K. Jain, K. Wayne Current, Paul J. Hurst

Proceedings of the IEEE International Conference on Acoustics, 1989

1988

A unified DCT/IDCT architecture for VLSI implementation.

J. R. Parkhurst, K. Wayne Current, Anil K. Jain, J. E. Grishaw

Proceedings of the IEEE International Conference on Acoustics, 1988

1986

Characteristics of Prototype CMOS Quaternary Logic Encoder-Decoder Circuits.

James L. Mangin, K. Wayne Current

IEEE Trans. Computers, 1986

1985

Response change in linearized circuits and systems: Computational algorithms and applications.

Stephen B. Haley, K. Wayne Current

Proc. IEEE, 1985

1980

A High Data-Rate Digital Output Correlator Design.

K. Wayne Current

IEEE Trans. Computers, 1980

Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders.

K. Wayne Current

IEEE Trans. Computers, 1980

High Density Integrated Computing Circuitry with Multiple Valued Logic.

K. Wayne Current

IEEE Trans. Computers, 1980

1979

Implementing Parallel Counters with Four-Valued Threshold Logic.

K. Wayne Current, Douglas A. Mow

IEEE Trans. Computers, 1979

A high data rate, low power all-digital correlation circuit design.

K. Wayne Current, Douglas A. Mow, S. Youssef-Digaleh

Proceedings of the IEEE International Conference on Acoustics, 1979

1978

Applications of multivalued threshold logic in large-scale-intergrated, digital signal processing circuits.

K. Wayne Current, Douglas A. Mow

Proceedings of the eighth international symposium on Multiple-valued logic, 1978

Four-valued threshold logic full adder circuit implementations.

K. Wayne Current, Douglas A. Mow

Proceedings of the eighth international symposium on Multiple-valued logic, 1978

Parallel counter design using four-valued threshold logic.

K. Wayne Current, Douglas A. Mow

Proceedings of the IEEE International Conference on Acoustics, 1978