Junjie Mu
Orcid: 0000-0002-6496-6539
According to our database1,
Junjie Mu
authored at least 18 papers
between 2020 and 2024.
Collaborative distances:
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Bibliography
2024
A 1-Mb RRAM Macro With 9.8 ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024
2023
Medical Biol. Eng. Comput., September, 2023
BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023
A Dynamic-Precision Bit-Serial Computing Hardware Accelerator for Solving Partial Differential Equations Using Finite Difference Method.
IEEE J. Solid State Circuits, February, 2023
A Time-Domain Wavefront Computing Accelerator With a 32 × 32 Reconfigurable PE Array.
IEEE J. Solid State Circuits, 2023
A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Graph-Based Accelerator of Retinex Model with Bit-Serial Computing for Image Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A Continuous-Time Ising Machine using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems.
IEEE J. Solid State Circuits, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference Method.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
A 20x28 Spins Hybrid In-Memory Annealing Computer Featuring Voltage-Mode Analog Spin Operator for Solving Combinatorial Optimization Problems.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 21×21 Dynamic-Precision Bit-Serial Computing Graph Accelerator for Solving Partial Differential Equations Using Finite Difference Method.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 252 Spins Scalable CMOS Ising Chip Featuring Sparse and Reconfigurable Spin Interconnects for Combinatorial Optimization Problems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
A 65nm Logic-Compatible Embedded and Flash Memory for In-Memory Computation of Artificial Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020