Jien-Chung Lo

According to our database1, Jien-Chung Lo authored at least 47 papers between 1988 and 2006.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2006
Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC).
IEEE Trans. Computers, 2006

An indirect current sensing technique for IDDQ and IDDT tests.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Equivalent IDDQ Tests for Systems with Regulated Power Supply.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005
On-chip short-time interval measurement system for high-speed signal timing characterization.
J. Syst. Archit., 2005

Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004
Efficient Realization of Parity Prediction Functions in FPGAs.
J. Electron. Test., 2004

Delay chain based programmable jitter generator.
Proceedings of the 9th European Test Symposium, 2004

2003
Time-to-voltage converter for on-chip jitter measurement.
IEEE Trans. Instrum. Meas., 2003

A Novel Technology Mapping Method for AND/XOR Expressions.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

On-Chip Short-Time Interval Measurement for High-Speed Signal Timing Characterization.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
Analysis of a BICS-Only Concurrent Error Detection Method.
IEEE Trans. Computers, 2002

Studies of the SEMATECH IDDq test data.
J. Syst. Archit., 2002

Efficient Decomposition Techniques for FPGAs.
Proceedings of the High Performance Computing, 2002

On-Chip Jitter Measurement for Phase Locked Loops.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
Using Atomic Force Microscopy for Deep-Submicron Failure Analysis.
IEEE Des. Test Comput., 2001

Efficient Parity Prediction in FPGA.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
Building Real Computer Systems.
IEEE Micro, 2000

Intermediacy Prediction for High Speed Berger Code Checkers.
J. Electron. Test., 2000

The 2nd Order Analysis of IDDQ Test Data.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

1999
Erasure Error Correction with Hardware Detection.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1998
A Case Study of Self-Checking Circuits Reliability.
VLSI Design, 1998

Correction to "A Fast Binary Adder with Conditional Carry Generation" IEEE Transaction on Computers 46(2) 248-253 (1997).
IEEE Trans. Computers, 1998

Online Current Testing.
IEEE Des. Test Comput., 1998

Highly Reliable Systems with Differential Built-In Current Sensors.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Challenges of Built-In Current Sensor Designs.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1997
A Fast Binary Adder with Conditional Carry Generation.
IEEE Trans. Computers, 1997

Fast and area-time efficient Berger code checkers.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996
Probability to Achieve TSC Goal.
IEEE Trans. Computers, 1996

A Hyper Optimal Encoding Scheme for Self-Checking Circuits.
IEEE Trans. Computers, 1996

Test Sequence Generation for Realistic Faults in CMOS ICs Based on Standard Cell Library.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Reliable Logic Circuits with Byte Error Control Codes: A Feasibility Study.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995
A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Single fault masking logic designs with error correcting codes.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1994
A concurrent error detection IC in 2-μm static CMOS logic.
IEEE J. Solid State Circuits, May, 1994

Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands.
IEEE Trans. Computers, 1994

1993
Novel Totally Self-Checking Berger Code Checker Designs Based on Generalized Berger Code Partitioning.
IEEE Trans. Computers, 1993

Berger Check Prediction for Array Multipliers and Array Dividers.
IEEE Trans. Computers, 1993

Fault-Tolerant Content Addressable Memory.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

A Probabilistic Measurement for Totally Self-Checking Circuits.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992
An SFS Berger check prediction ALU and its application to self-checking processor designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

On-chip current sensing circuit for CMOS VLSI.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Reliable Floating-Point Arithmetic Algorithms for Berger Encoded Operands.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Design of Static CMOS Self-Checking Circuits using Built-In Current Sensing.
Proceedings of the Digest of Papers: FTCS-22, 1992

1991
A new protocol for efficient bandwidth distribution in integrated service networks.
Proceedings of the 16th Conference on Local Computer Networks, 1991

1990
On the Design of Combinational Totally Self-Checking I-out-of3 Code Checkers.
IEEE Trans. Computers, 1990

1989
Concurrent error detection in arithmetic and logical operations using Berger codes.
Proceedings of the 9th Symposium on Computer Arithmetic, 1989

1988
The design of fast totally self-checking Berger code checkers based on Berger code partitioning.
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988


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