Jianyi Cheng

Yiren Zhao

CoRR, 2024

SEER: Super-Optimization Explorer for High-Level Synthesis using E-graph Rewriting.

[BibT_eX]

[DOI]

Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023

Parallelising Control Flow in Dynamic-scheduling High-level Synthesis.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., December, 2023

Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets.

[BibT_eX]

[DOI]

Estíbaliz Fraca

IEEE Trans. Computers, November, 2023

GSA to HDL: Towards principled generation of dynamically scheduled circuits.

[BibT_eX]

[DOI]

Aditya Rajagopal

Diederik Adriaan Vink

Yann Herklotz

CoRR, 2023

SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR.

[BibT_eX]

[DOI]

CoRR, 2023

Fast Prototyping Next-Generation Accelerators for New ML Models using MASE: ML Accelerator System Exploration.

[BibT_eX]

[DOI]

Alexander Montgomerie-Corcoran

Cheng Zhang

Zhewen Yu

Can Xiao

Christos-Savvas Bouganis

Yiren Zhao

CoRR, 2023

PASS: Exploiting Post-Activation Sparsity in Streaming Architectures for CNN Acceleration.

[BibT_eX]

[DOI]

Alexander Montgomerie-Corcoran

Zhewen Yu

Christos-Savvas Bouganis

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference?

[BibT_eX]

[DOI]

Cheng Zhang

Ilia Shumailov

Yiren Zhao

Proceedings of the 2023 Conference on Empirical Methods in Natural Language Processing, 2023

2022

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis.

[BibT_eX]

[DOI]

Paolo Ienne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

Area-Efficient Memory Scheduling for Dynamically Scheduled High-Level Synthesis.

[BibT_eX]

[DOI]

Xuefei He

Proceedings of the International Conference on Field-Programmable Technology, 2022

POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations.

[BibT_eX]

[DOI]

Ruizhe Zhao

Wayne Luk

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Dynamic Inter-Block Scheduling for HLS.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Finding and Finessing Static Islands in Dynamically Scheduled Circuits.

[BibT_eX]

[DOI]

Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

Dynamic C-Slow Pipelining for HLS.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

2021

ScaleHLS: Scalable High-Level Synthesis through MLIR.

[BibT_eX]

[DOI]

CoRR, 2021

Phism: Polyhedral High-Level Synthesis in MLIR.

[BibT_eX]

[DOI]

Ruizhe Zhao

CoRR, 2021

A Concept Knowledge-Driven Keywords Retrieval Framework for Sponsored Search.

[BibT_eX]

[DOI]

CoRR, 2021

Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLS.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Probabilistic Optimization for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Probabilistic Scheduling in High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020

Combining Dynamic & Static Scheduling in High-level Synthesis.

[BibT_eX]

[DOI]

Paolo Ienne

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019

EASY: Efficient Arbiter SYnthesis from Multi-threaded Code.

[BibT_eX]

[DOI]