Jianan Mu
Orcid: 0000-0001-8513-0792
According to our database1,
Jianan Mu
authored at least 5 papers
between 2022 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023
Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants.
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023
2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022