Jared Stark

Orcid: 0009-0002-4366-4723

According to our database1, Jared Stark authored at least 23 papers between 1996 and 2024.

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Bibliography

2024
PDIP: Priority Directed Instruction Prefetching.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
EMISSARY: Enhanced Miss Awareness Replacement Policy for L2 Instruction Caching.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2019
Towards the adoption of Local Branch Predictors in Modern Out-of-Order Superscalar Processors.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

2014
Author retrospective for bloom filtering cache misses for accurate data speculation and prefetching.
Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014

2006
Wish Branches: Enabling Adaptive and Aggressive Predicated Execution.
IEEE Micro, 2006

2005
Better Branch Prediction Through Prophet/Critic Hybrids.
IEEE Micro, 2005

Guest Editors Introduction.
J. Instr. Level Parallelism, 2005

On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor.
IEEE Comput. Archit. Lett., 2005

Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution.
Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005

2004
Prophet/Critic Hybrid Branch Prediction.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

2003
Runahead Execution: An Effective Alternative to Large Instruction Windows.
IEEE Micro, 2003

Improving Branch Prediction by Dynamic Dataflow-Based Identification of Correlated Branches from a Large Global History.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

2002
Bloom filtering cache misses for accurate data speculation and prefetching.
Proceedings of the 16th international conference on Supercomputing, 2002

2001
Select-free instruction scheduling logic.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

2000
Out-of-order fetch, decode, and issue.
PhD thesis, 2000

On pipelining dynamic instruction scheduling logic.
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

1999
Simultaneous Subordinate Microthreading (SSMT).
Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999

1998
Variable Length Path Branch Prediction.
Proceedings of the ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, 1998

1997
Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution.
Int. J. Parallel Program., 1997

One Billion Transistors, One Uniprocessor, One Chip.
Computer, 1997

Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order.
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

1996
The effects of mispredicted-path execution on branch prediction structures.
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996


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