James H. Mulligan Jr.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1995

Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay.

[BibT_eX]

[DOI]

Tolga Soyata

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994

Optimization of phase-locked loop performance in data recovery systems.

[BibT_eX]

[DOI]

Ramon S. Co

IEEE J. Solid State Circuits, September, 1994

1993

Multiple training concept for back-propagation neural networks for use in associative memories.

[BibT_eX]

[DOI]

Neural Networks, 1993

Integration of Clock Skew and Register Delays into a Retiming Algorithm.

[BibT_eX]

Tolga Soyata

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1991

Clock frequency and latency in synchronous digital systems.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 1991

Guaranteed recall of all training pairs for bidirectional associative memory.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks, 1991

1990

On multiple training for bidirectional associative memory.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks, 1990

Two coding strategies for bidirectional associative memory.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks, 1990

1959

A Figure of Merit for Single-Pass Data Recording Systems.

[BibT_eX]

[DOI]