Jaehun Jeong

Orcid: 0000-0001-6323-4830

According to our database1, Jaehun Jeong authored at least 19 papers between 2012 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Highly Reliable/Manufacturable 4nm FinFET Platform Technology (SF4X) for HPC Application with Dual-CPP/HP-HD Standard Cells.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

World's First GAA 3nm Foundry platform Technology (SF3) with Novel Multi-Bridge-Channel-FET (MBCFET™) Process.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Compact Design of SPAD Detector with Quenching Circuit for Reduced Dark Count Rate.
Proceedings of the 20th International SoC Design Conference, 2023

A 12-bit 5MS/s Synchronous SAR ADC With Comparator Using High Gain Pre-amplifier.
Proceedings of the 20th International SoC Design Conference, 2023

A 8-bit DPWM-based Analog Bypass Circuit and System for LED Matrix Headlamp in High-Voltage 180-nm CMOS Technology.
Proceedings of the 20th International SoC Design Conference, 2023

2022
An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2020
2.4 A 7nm High-Performance and Energy-Efficient Mobile Application Processor with Tri-Cluster CPUs and a Sparsity-Aware NPU.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Continuous-Time Bandpass Delta-Sigma Modulators and Bitstream Processing: (Invited).
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
A 1-GHz 16-Element Four-Beam True-Time-Delay Digital Beamformer.
IEEE J. Solid State Circuits, 2019

2018
A 16-Element 4-Beam 1 GHz IF 100 MHz Bandwidth Interleaved Bit Stream Digital Beamformer in 40 nm CMOS.
IEEE J. Solid State Circuits, 2018

2017
A multi-objective evolutionary approach to automatic melody generation.
Expert Syst. Appl., 2017

2016
A 260 MHz IF Sampling Bit-Stream Processing Digital Beamformer With an Integrated Array of Continuous-Time Band-Pass ΔΣ Modulators.
IEEE J. Solid State Circuits, 2016

A Multi-agent System for Creating Art Based on Boids with Evolutionary and Neural Networks.
Proceedings of the Bio-inspired Computing - Theories and Applications, 2016

2015
An Evolutionary Approach to Generate Rhythm and Melody Based on Repertories.
Proceedings of the Bio-Inspired Computing - Theories and Applications, 2015

PSO Optimized Multipurpose Image Watermarking Using SVD and Chaotic Sequence.
Proceedings of the Bio-Inspired Computing - Theories and Applications, 2015

2014
A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management.
IEEE J. Solid State Circuits, 2014

A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF.
IEEE J. Solid State Circuits, 2014

2012
A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-way wireless telemetry for treatment of neurological disorders.
Proceedings of the Symposium on VLSI Circuits, 2012

A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012


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