Ismail Bustany

Orcid: 0000-0002-7099-1546

According to our database¹, Ismail Bustany authored at least 27 papers between 2004 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

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PhD thesis

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Links

On csauthors.net:

Bibliography

2024

K-SpecPart: Supervised Embedding Algorithms and Cut Overlay for Improved Hypergraph Partitioning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

Calibration-Based Differentiable Timing Optimization in Non-linear Global Placement.

[BibT_eX]

[DOI]

Proceedings of the 2024 International Symposium on Physical Design, 2024

2023

Entropy Maximization in Sparse Matrix by Vector Multiplication (max<sub>E</sub>SpMV).

[BibT_eX]

[DOI]

CoRR, 2023

K-SpecPart: A Supervised Spectral Framework for Multi-Way Hypergraph Partitioning Solution Improvement.

[BibT_eX]

[DOI]

CoRR, 2023

The 2023 MLCAD FPGA Macro Placement Benchmark Design Suite and Contest Results.

[BibT_eX]

[DOI]

Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

An Open-Source Constraints-Driven General Partitioning Multi-Tool for VLSI Physical Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

RL-Ripper: : A Framework for Global Routing Using Reinforcement Learning and Smart Net Ripping Techniques.

[BibT_eX]

[DOI]

Upma Gandhi

Erfan Aghaeekiasaraee

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022

A Machine Learning Approach for Accelerating SimPL-Based Global Placement for FPGA's.

[BibT_eX]

[DOI]

Tianyi Yu

Nima Karimpour Darav

Ismail Bustany

Mehrdad Eslami Dehkordi

Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, 2022

Machine-Learning Based Delay Prediction for FPGA Technology Mapping.

[BibT_eX]

[DOI]

Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, 2022

SpecPart: A Supervised Spectral Framework for Hypergraph Partitioning Solution Improvement.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021

Still Benchmarking After All These Years.

[BibT_eX]

[DOI]

Ismail S. Bustany

Jinwook Jung

Patrick H. Madden

Natarajan Viswanathan

Stephen Yang

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

2020

Eh?Predictor: A Deep Learning Framework to Identify Detailed Routing Short Violations From a Placed Netlist.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

From Tuning to Learning: Why the FPGA Physical Design Flow Offers a Compelling Case for ML?

[BibT_eX]

[DOI]

Ismail S. Bustany

Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

2019

Session details: Keynote.

[BibT_eX]

[DOI]

Ismail Bustany

Proceedings of the 2019 International Symposium on Physical Design, 2019

2018

Eh?Legalizer: A High Performance Standard-Cell Legalizer Observing Technology Constraints.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2018

NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A machine learning framework to identify detailed routing short violations from a placed netlist.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum Movement.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

ICCAD-2017 CAD contest in multi-deck standard cell legalization and benchmarks.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016

Method of Outer Approximations and Adaptive Approximations for a Class of Matrix Games.

[BibT_eX]

[DOI]

J. Optim. Theory Appl., 2016

2015

POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

The impact of industry-organized contests on EDA education.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Microelectronics Systems Education, 2015

ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement.

[BibT_eX]

[DOI]

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

2014

ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2014

2013

POLAR: placement based on novel rough legalization and refinement.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

The nature of optimization problem challenges in physical synthesis.

[BibT_eX]

[DOI]

Ismail Bustany

Igor L. Markov

Martin D. F. Wong

Proceedings of the American Control Conference, 2013

2004

Performance Tuning of Matrix Triple Products Based on Matrix Structure.

[BibT_eX]

[DOI]

Proceedings of the Applied Parallel Computing, 2004

Ismail Bustany

Timeline

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On csauthors.net:

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