Ibrahim Hur

Orcid: 0009-0003-8375-3963

According to our database1, Ibrahim Hur authored at least 46 papers between 2004 and 2024.

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Bibliography

2024
Accurate and Scalable Many-Node Simulation.
CoRR, 2024

HotTiles: Accelerating SpMM with Heterogeneous Accelerator Architectures.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor.
IEEE Micro, 2023

Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

2022
Efficient Asynchronous RPC Calls for Microservices: DeathStarBench Study.
CoRR, 2022

DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

Towards a GraphBLAS Implementation for Go.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

2021
Automatic Sublining for Efficient Sparse Memory Accesses.
ACM Trans. Archit. Code Optim., 2021

RIO: ROB-Centric In-Order Modeling of Out-of-Order Processors.
IEEE Comput. Archit. Lett., 2021

Modeling DRAM Timing in Parallel Simulators With Immediate-Response Memory Model.
IEEE Comput. Archit. Lett., 2021

Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2020
PIUMA: Programmable Integrated Unified Memory Architecture.
CoRR, 2020

Breaking In-Order Branch Miss Recovery.
IEEE Comput. Archit. Lett., 2020

Hash Table Scalability on Intel PIUMA.
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

Projecting Performance for PIUMA using Down-Scaled Simulation.
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

Efficient Sparse Matrix-Vector Multiplication on Intel PIUMA Architecture.
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

2018
Multi-Stage CPI Stacks.
IEEE Comput. Archit. Lett., 2018

Many-core graph workload analysis.
Proceedings of the International Conference for High Performance Computing, 2018

Extending the Performance Analysis Tool Box: Multi-stage CPI Stacks and FLOPS Stacks.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

Near-side prefetch throttling: adaptive prefetching for high-performance many-core processors.
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018

2017
Exploring optimizations on shared-memory platforms for parallel triangle counting algorithms.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

2015
Initial results on computational performance of Intel many integrated core, sandy bridge, and graphical processing unit architectures: implementation of a 1D c++/OpenMP electrostatic particle-in-cell code.
Concurr. Comput. Pract. Exp., 2015

2014
An Evaluation of High-Level Mechanistic Core Models.
ACM Trans. Archit. Code Optim., 2014

Automatic SMT threading for OpenMP applications on the Intel Xeon Phi co-processor.
Proceedings of the 4th International Workshop on Runtime and Operating Systems for Supercomputers, 2014

Undersubscribed threading on clustered cache architectures.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2012
Hardware transactional memory with software-defined conflicts.
ACM Trans. Archit. Code Optim., 2012

Resource-bounded multicore emulation using Beefarm.
Microprocess. Microsystems, 2012

Circuit design of a dual-versioning L1 data cache.
Integr., 2012

Profiling and Optimizing Transactional Memory Applications.
Int. J. Parallel Program., 2012

Power-aware multi-core simulation for early design stage hardware/software co-optimization.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only).
SIGMETRICS Perform. Evaluation Rev., 2011

RMS-TM: a comprehensive benchmark suite for transactional memory systems.
Proceedings of the ICPE'11, 2011

Circuit design of a dual-versioning L1 data cache for optimistic concurrency.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
The Velox Transactional Memory Stack.
IEEE Micro, 2010

Discovering and understanding performance bottlenecks in transactional applications.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
Feedback mechanisms for improving probabilistic memory prefetching.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

2008
A comprehensive approach to DRAM power management.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

2007
Memory scheduling for modern microprocessors.
ACM Trans. Comput. Syst., 2007

2006
Adaptive History-Based Memory Schedulers for Modern Processors.
IEEE Micro, 2006

Memory Prefetching Using Adaptive Stream Detection.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

2004
Adaptive History-Based Memory Schedulers.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004


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