Hugo De Man

Affiliations:
  • KU Leuven, Belgium


According to our database1, Hugo De Man authored at least 277 papers between 1983 and 2013.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 1986, "For contributions to simulation, analysis and optimization of devices, MOS circuits, and sampled data systems.".

Timeline

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Bibliography

2013
Panel: the heritage of Mead & Conway: what has remained the same, what was missed, what has changed, what lies ahead.
Proceedings of the Design, Automation and Test in Europe, 2013

2011
Beyond the horizon: The next 10x reduction in power - Challenges and solutions.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
Panel session - great challenges in nanoelectronics and impact on academic research: More than Moore or Beyond CMOS?
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Reed-solomon codes implementing a coded single-carrier with cyclic prefix scheme.
IEEE Trans. Commun., 2009

Efficient computation of symbol statistics from bit a priori information in turbo receivers.
IEEE Trans. Commun., 2009

2007
Filterbank Decompositions for (Non)-Systematic Reed-Solomon Codes With Applications to Soft Decoding.
IEEE Trans. Signal Process., 2007

Scalable Gate-Level Models for Power and Timing Analysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
SWAN: high-level simulation methodology for digital substrate noise generation.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Critically Subsampled Filterbanks for SISO Reed-Solomon Decoding.
IEEE Trans. Signal Process., 2006

Evolution of substrate noise generation mechanisms with CMOS technology scaling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Combining Reed-Solomon Codes and OFDM for Impulse Noise Mitigation: RS-OFDM.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

Reed-Solomon Codes Implementing a Coded OFDM Scheme for Rayleigh Fading Channels.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

2005
Compensation of IQ imbalance and phase noise in OFDM systems.
IEEE Trans. Wirel. Commun., 2005

Digital ground bounce reduction by supply current shaping and clock frequency Modulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications.
IEEE Trans. Computers, 2005

Soft-in soft-out Reed-Solomon decoding using critically subsampled filterbanks.
Proceedings of the IEEE ITSOC Information Theory Workshop 2005 on Coding and Complexity, 2005

Filterbank decompositions for BCH-codes with applications to soft decoding and code division multiple acces systems.
Proceedings of the 2005 IEEE International Symposium on Information Theory, 2005

IIR critically subsampled filterbanks implementing systematic Reed-Solomon codes.
Proceedings of IEEE International Conference on Communications, 2005

Critically subsampled filterbanks implementing Reed-Solomon codes: an algebraic point of view.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

On the impact of multi-antenna RF transceivers' amplitude and phase mismatches on transmit MRC.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

2004
Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors.
J. VLSI Signal Process., 2004

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate.
IEEE J. Solid State Circuits, 2004

Joint compensation of IQ imbalance, frequency offset and phase noise in OFDM receivers.
Eur. Trans. Telecommun., 2004

OFDM versus Single Carrier: A Realistic Multi-Antenna Comparison.
EURASIP J. Adv. Signal Process., 2004

Multicarrier Block-Spread CDMA for Broadband Cellular Downlink.
EURASIP J. Adv. Signal Process., 2004

Spatial-Mode Selection for the Joint Transmit and Receive MMSE Design.
EURASIP J. Adv. Signal Process., 2004

Connecting E-Dreams to Deep-Submicron Realities.
Proceedings of the Integrated Circuit and System Design, 2004

Compensation of transmitter IQ imbalance for OFDM systems.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

A single-carrier/OFDM comparison for broadband wireless communication.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Critically subsampled filterbanks implementing Reed-Solomon codes.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

A robust joint linear precoder and decoder MMSE design for slowly time-varying MIMO channels.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

OFDM vs. single-carrier: a multi-antenna comparison.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Turbo-like soft-decision decoding of Reed-Solomon codes.
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004

Digital Ground Bounce Reduction by Phase Modulation of the Clock.
Proceedings of the 2004 Design, 2004

Were the good old days all that good?: EDA then and now.
Proceedings of the 41th Design Automation Conference, 2004

High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects.
Proceedings of the 41th Design Automation Conference, 2004

Embedded systems education: how to teach the required skills?
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs].
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Constrained least squares detector for OFDM/SDMA-based wireless networks.
IEEE Trans. Wirel. Commun., 2003

Power-efficient flexible processor architecture for embedded applications.
IEEE Trans. Very Large Scale Integr. Syst., 2003

PeopleMover: an example of interdisciplinary project-based education in electrical engineering.
IEEE Trans. Educ., 2003

An analytic Volterra-series-based model for a MEMS variable capacitor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies.
IEEE J. Solid State Circuits, 2003

Space-time block coding for single-carrier block transmission DS-CDMA downlink.
IEEE J. Sel. Areas Commun., 2003

Entwurf von Nanosystemen für Ambient Intelligence (Designing Nano-Scale Systems for the Ambient-Intelligence World).
it Inf. Technol., 2003

Efficient System-Level Functional Verification Methodology for Multimedia Applications.
IEEE Des. Test Comput., 2003

Systematic Application of Data Transfer and Storage Optimizing Code Transformations for Power Consumption and Execution Time Reduction in ACROPOLIS: A Pre-Compiler for Multimedia Applications.
Des. Autom. Embed. Syst., 2003

Global interconnect trade-off for technology over memory modules to application level: case study.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

Joint compensation of IQ imbalance and frequency offset in OFDM systems.
Proceedings of the Global Telecommunications Conference, 2003

ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

A linear high voltage charge pump for MEMs applications in 0.18μm CMOS technology.
Proceedings of the ESSCIRC 2003, 2003

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate.
Proceedings of the ESSCIRC 2003, 2003

Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling.
Proceedings of the 2003 Design, 2003

Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver.
Proceedings of the 2003 Design, 2003

2002
A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects.
J. Supercomput., 2002

System-level exploration of association table implementations in telecom network applications.
ACM Trans. Embed. Comput. Syst., 2002

Adaptive loading for OFDM/SDMA-based wireless networks.
IEEE Trans. Commun., 2002

Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification.
IEEE J. Solid State Circuits, 2002

Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits.
IEEE J. Solid State Circuits, 2002

Interconnect exploration for future wire dominated technologies.
Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002

DRESC: a retargetable compiler for coarse-grained reconfigurable architectures.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications.
Proceedings of the Field-Programmable Logic and Applications, 2002

On Nanoscale Integration and Gigascale Complexity in the Post.Com World.
Proceedings of the 2002 Design, 2002

Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients.
Proceedings of the 39th Design Automation Conference, 2002

2001
A Systematic Approach to Reduce the System Bus Load and Power in Multimedia Algorithms.
VLSI Design, 2001

80-Mb/s QPSK and 72-Mb/s 64-QAM flexible and scalable digital OFDM transceiver ASICs for wireless local area networks in the 5-GHz band.
IEEE J. Solid State Circuits, 2001

Space-time chip equalizer receivers for WCDMA forward link with time-multiplexed pilot.
Proceedings of the 54th IEEE Vehicular Technology Conference, 2001

A Systematic Approach for System Bus Load Reduction Applied to Medical Imaging.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Memory hierarchy layer assignment for data re-use exploitation in multimedia algorithms realized on predefined processor architectures.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Adaptive MMSE/pcPIC-MMSE multiuser detector for MC-CDMA satellite system.
Proceedings of the IEEE International Conference on Communications, 2001

Semi-blind space-time chip equalizer receivers for WCDMA forward link with code-multiplexed pilot.
Proceedings of the IEEE International Conference on Acoustics, 2001

Solving large scale assignment problems in high-level synthesis by approximative quadratic programming.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware.
Proceedings of the Field-Programmable Logic and Applications, 2001

A SW/HW Interface API for Java/FPGA Co-Designed Applets.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

Task concurrency management methodology summary.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Cache conscious data layout organization for embedded multimedia applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

High-level simulation of substrate noise generation from large digital circuits with multiple supplies.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Virtual Java/FPGA interface for networked reconfiguration.
Proceedings of ASP-DAC 2001, 2001

2000
A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints.
J. VLSI Signal Process., 2000

Formalized three-layer system-level model and reuse methodology for embedded data-dominated applications.
IEEE Trans. Very Large Scale Integr. Syst., 2000

A combined OFDM/SDMA approach.
IEEE J. Sel. Areas Commun., 2000

A Hardware Virtual Machine for the Networked Reconfiguration.
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000

Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

A loop transformation approach for combined parallelization and data transfer and storage optimization.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform.
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000

Flexible hardware acceleration for multimedia oriented microprocessors.
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

Do our low-power tools have enough horse power? (panel session) (title only).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Advanced Data Layout Optimization for Multimedia Applications.
Proceedings of the Parallel and Distributed Processing, 2000

Task Concurrency Management Experiment for Power-Efficient Speed-up of Embedded MPEG4 IM1 Player.
Proceedings of the 2000 International Workshop on Parallel Processing, 2000

A single-carrier frequency-domain SDMA basestation.
Proceedings of the IEEE International Conference on Acoustics, 2000

Rethinking Engineering Research and Education for Post-PC Systems-on-a-Chip.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications.
Proceedings of the 2000 Design, 2000

Operating system based software generation for systems-on-chip.
Proceedings of the 37th Conference on Design Automation, 2000

Extended design reuse trade-offs in hardware-software architecture mapping.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

A preprocessing step for global loop transformations for data transfer optimization.
Proceedings of the 2000 International Conference on Compilers, 2000

1999
Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management.
J. VLSI Signal Process., 1999

Guest Editors' Introduction.
J. VLSI Signal Process., 1999

System-Level Energy-Delay Exploration for Multimedia Applications on Embedded Cores with Hardware Cache.
J. VLSI Signal Process., 1999

Minimizing the required memory bandwidth in VLSI system realizations.
IEEE Trans. Very Large Scale Integr. Syst., 1999

An efficient VLSI architecture for 2-D wavelet image coding with novel image scan.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Strategy for power-efficient design of parallel systems.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Low Power Memory Storage and Transfer Organization for the MPEG-4 Full Pel Motion Estimation on a Multimedia Processor.
IEEE Trans. Multim., 1999

Strategy for power efficient combined task and data parallelism exploration illustrated on a QSDPCM video codec.
J. Syst. Archit., 1999

System-on-Chip Design: Impact on Education and Research.
IEEE Des. Test Comput., 1999

Design Technology Research and Education for Deep-Submicron Systems of the Next Century.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Platform Independent Data Transfer and Storage Exploration Illustrated on Parallel Cavity Detection Algorithm.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

Exploration and Synthesis of Dynamic Data Sets in Telecom Network Applications.
Proceedings of the 12th International Symposium on System Synthesis, 1999

A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

A Single-Package Solution for Wireless Transceivers.
Proceedings of the 1999 Design, 1999

Timed executable system specification of an ADSL modem using a C++ based design environment: a case study.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
System-Level Power Optimization of Video Codecs on Embedded Cores: A Systematic Approach.
J. VLSI Signal Process., 1998

System-Level Data-Flow Transformation Exploration and Power-Area Trade-offs Demonstrated on Video Codecs.
J. VLSI Signal Process., 1998

Formalized methodology for data reuse: exploration for low-power hierarchical memory mappings.
IEEE Trans. Very Large Scale Integr. Syst., 1998

High-level address optimization and synthesis techniques for data-transfer-intensive applications.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Program transformation strategies for memory size and power reduction of pseudoregular multimedia subsystems.
IEEE Trans. Circuits Syst. Video Technol., 1998

Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation.
J. Electron. Test., 1998

Invited Address: Future Systems-on-a-Chip: Impact on Engineering Education.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Power exploration for dynamic data types through virtual memory management refinement.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Code Transformations for Low Power Caching in Embedded Multimedia Processors.
Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998

Code Transformations for Reduced Data Transfer and Storage in Low Power Realisations of MPEG-4 Full-Pel Motion Estimation.
Proceedings of the 1998 IEEE International Conference on Image Processing, 1998

Hardware Cache Optimization for Parallel Multimedia Applications.
Proceedings of the Euro-Par '98 Parallel Processing, 1998

Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Synthesis of pipelined DSP accelerators with dynamic scheduling.
IEEE Trans. Very Large Scale Integr. Syst., 1997

Practical solutions for counting scalars and dependences in ATOMIUM-a memory management system for multidimensional signal processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Hardware/software co-design of digital telecommunication systems.
Proc. IEEE, 1997

Memory Size Reduction Through Storage Order Optimization for Embedded Parallel Multimedia Applications.
Parallel Comput., 1997

Formalized methodology for data reuse exploration in hierarchical memory mappings.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

A System Design Methodology for Telecommunication Network Applications.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Multi-thread graph: a system model for real-time embedded software synthesis.
Proceedings of the European Design and Test Conference, 1997

Architectural exploration and optimization for counter based hardware address generation.
Proceedings of the European Design and Test Conference, 1997

Education for the Deep Submicron Age: Business as Usual?
Proceedings of the 34st Conference on Design Automation, 1997

System level memory optimization for hardware-software co-design.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

Array Placement for Storage Size Reduction in Embedded Multimedia Systems.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996
Transforming set data types to power optimal data structures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Submicron design tools: problems and suppliers.
IEEE Des. Test Comput., 1996

CoWare - A design environment for heterogeneous hardware/software systems.
Des. Autom. Embed. Syst., 1996

Designing Systems On Silicon: A Digital Spread Spectrum Pager.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Flow Graph Balancing for Minimizing the Required Memory Bandwidth.
Proceedings of the 9th International Symposium on System Synthesis, 1996

ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures.
Proceedings of the 9th International Symposium on System Synthesis, 1996

Power exploration for data dominated video applications.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

System-level data-flow transformations for power reduction in image and video processing.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

A Hilbert fractal codec for region oriented compression of color images.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

System-Level Memory Management for Weakly Parallel Image Processing.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

CoWare - a design environment for heterogenous hardware/software systems.
Proceedings of the conference on European design automation, 1996

A Graph Based Processor Model for Retargetable Code Generation.
Proceedings of the 1996 European Design and Test Conference, 1996

A Specification Invariant Technique for Regularity Improvement between Flow-Graph Clusters.
Proceedings of the 1996 European Design and Test Conference, 1996

A Strategy for Real-Time Kernel Support in Application-Specific HW/SW Embedded Architectures.
Proceedings of the 33st Conference on Design Automation, 1996

Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications.
Proceedings of the 33st Conference on Design Automation, 1996

Embedded Architecture Co-Synthesis and System Integration.
Proceedings of the Forth International Workshop on Hardware/Software Codesign, 1996

1995
Formalisation of multi-precision arithmetic for high-level synthesis of DSP architectures.
J. VLSI Signal Process., 1995

Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures.
J. VLSI Signal Process., 1995

Background memory area estimation for multidimensional signal processing systems.
IEEE Trans. Very Large Scale Integr. Syst., 1995

Quadratic zero-one programming-based synthesis of application-specific data paths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Mapping real-time motion estimation type algorithms to memory efficient, programmable multi-processor architectures.
Microprocess. Microprogramming, 1995

Partial scan and symbolic test at the register-transfer level.
J. Electron. Test., 1995

Software Synthesis for Real-Time Information Processing Systems.
Proceedings of the ACM SIGPLAN 1995 Workshop on Languages, 1995

Real-time multi-tasking in software synthesis for information processing systems.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

System level verification of video and image processing specifications.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Memory organization for video algorithms on programmable signal processors.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Improving DSP design expertise by stepwise educational intensification.
Proceedings of the 1995 International Conference on Acoustics, 1995

Search space reduction through clustering in test generation.
Proceedings of the Proceedings EURO-DAC'95, 1995

Timing optimization by bit-level arithmetic transformations.
Proceedings of the Proceedings EURO-DAC'95, 1995

A unified scheduling model for high-level synthesis and code generation.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
A generalized state assignment theory for transformations on signal transition graphs.
J. VLSI Signal Process., 1994

Cellular automata based deterministic self-test strategies for programmable data paths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Transformation of Nested Loops with Modulo Indexing to Affine Recurrences.
Parallel Process. Lett., 1994

Scheduling with register constraints for DSP architectures.
Integr., 1994

A Proof of the Nonrestoring Division Algorithm and its Implementation on an ALU.
Formal Methods Syst. Des., 1994

Modeling Multi-rate DSP Specification Semantics for Formal Transformational Design in HOL.
Formal Methods Syst. Des., 1994

Design of a C-testable booth multiplier using a realistic fault model.
J. Electron. Test., 1994

Reasoning About a Class of Linear Systems of Equations in HOL.
Proceedings of the Higher Order Logic Theorem Proving and Its Applications, 1994

Bit-alignment for retargetable code generators.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Instruction set definition and instruction selection for ASIPs.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Data routing: a paradigm for efficient data-path synthesis and code generation.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

A specification invariant technique for operation cost minimisation in flow-graphs.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

ASP 12: Forum - Analog Electronics - a European Speciality?
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Parallel Method for Functional Verification of Medium and High Throughput DSP Synthesis.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Dataflow-driven memory allocation for multi-dimensional signal processing systems.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

A Generalized Signal Transition Graph Model for Specification of Complex Interfaces.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Signal Type Optimisation in the Design of Time-Multiplexed DSP Architectures.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Control flow optimization for fast system simulation and storage minimization.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

A Time Abstraction Method for Efficient Verification of Communicating Systems.
Proceedings of the 31st Conference on Design Automation, 1994

An optimisation methodology for array mapping of affine recurrence equations in video and image processing.
Proceedings of the International Conference on Application Specific Array Processors, 1994

Loop transformation methodology for fixed-rate video, image and telecom processing applications.
Proceedings of the International Conference on Application Specific Array Processors, 1994

1993
An application-specific architecture for the RBN-coder with efficient memory organization.
J. VLSI Signal Process., 1993

Modeling multidimensional data and control flow.
IEEE Trans. Very Large Scale Integr. Syst., 1993

On the Comparison of HOL and Boyer-Moore for Formal Hardware Verification.
Formal Methods Syst. Des., 1993

Testability analysis in high level data path synthesis.
J. Electron. Test., 1993

Test Algorithms for Double-Buffered Random Access and Pointer-Addressed Memories.
IEEE Des. Test Comput., 1993

Degrees of Formality in Shallow Embedding Hardware Description Languages in HOL.
Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1993

Partial Scan at the Register-Transfer Level.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Low-Power Driven Technology Mapping under Timing Constraints.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Sizing and verification of communication buffers for communicating processes.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Exact evaluation of memory size for multi-dimensional signal processing systems.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

An Architecture for Ray - Bezier Patch Intersection.
Proceedings of the EGGH93: Eurographics Workshop on Graphics Hardware 1993, 1993

High-level synthesis for real-time digital signal processing.
The Kluwer international series in engineering and computer science 216, Kluwer, ISBN: 978-0-7923-9313-9, 1993

1992
Nonlinear transformations for high level regular array ASIC synthesis.
J. VLSI Signal Process., 1992

Optimized synthesis of asynchronous control circuits from graph-theoretic specifications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Combined hardware selection and pipelining in high-performance data-path design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

The Formal Semantics Definition of a Multi-Rate DSP Specification Language in HOL.
Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1992

A Description Methodology for Parameterized Modules in the Boyer-Moore Logic.
Proceedings of the Theorem Provers in Circuit Design, 1992

Optimized BIST Strategies for Programmable Data Paths Based on Cellular Automata.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

A Proof of the Non-Restoring Division Algorithm and its Implementation on the Cathedral-II ALU.
Proceedings of the Designing Correct Circuits, 1992

Flag/Condition Handling and Branch Assignment for Large Microcoded Controllers.
Proceedings of the Synthesis for Control Dominated Circuits, 1992

Regular Module Generation or Standard Cells: Two Alternative Implementations of a Library of Functional Building Blocks.
Proceedings of the Synthesis for Control Dominated Circuits, 1992

Performance Through Hierarchy in Static Timing Verification.
Proceedings of the Algorithms, Software, Architecture, 1992

Just in Time Scheduling.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

A generalized state assignment theory for transformation on signal transition graphs.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Models for bit-true simulation and high-level synthesis of DSP applications.
Proceedings of the Second Great Lakes Symposium on VLSI, 1992

On the use of hierarchy in timing verification with statically sensitizable paths.
Proceedings of the Second Great Lakes Symposium on VLSI, 1992

Design technology research for the nineties: more of the same?
Proceedings of the conference on European design automation, 1992

ASICs for a High Performance IVIulti Processor Systemfor Photo-realistic Image Synthesis.
Proceedings of the EGGH92: Eurographics Workshop on Graphics Hardware 1992, 1992

Time Constrained Allocation and Assignment Techniques for High Throughput Signal Processing.
Proceedings of the 29th Design Automation Conference, 1992

1991
In-place memory management of algebraic algorithms on application specific ICs.
J. VLSI Signal Process., 1991

Synthesis of ASIC regular arrays for real-time image processing systems.
J. VLSI Signal Process., 1991

DARSI: RC data reduction [VLSI simulation].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Partitioning-Based Allocation of Dedicated Data-Paths in the Architectural Synthesis for High Throughput Applications.
Proceedings of the VLSI 91, 1991

Defining Recursive Functions in HOL.
Proceedings of the 1991 International Workshop on the HOL Theorem Proving System and its Applications, 1991

Formal Hardware Verification in HOL and in Boyer-Moore: A Comparative Analysis.
Proceedings of the 1991 International Workshop on the HOL Theorem Proving System and its Applications, 1991

Illustration of the SFG-Tracing Multi-Level Behavioral Verification Methodology, by the Correctness Proof of a High to Low Level Synthesis Application in CATHEDRAL-II.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Compiling Multi-Dimensional Data Streams into Distributed DSP ASIC Memory.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Clustering Techniques for Register Optimization During Scheduling Preprocessing.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Breaking the bottleneck of sequential decoding for high-speed digital communication.
Proceedings of the 1991 International Conference on Acoustics, 1991

Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment.
Proceedings of the conference on European design automation, 1991

Affine transformations for multi-dimensional signal processing on ASIC regular arrays.
Proceedings of the conference on European design automation, 1991

Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications.
Proceedings of the 28th Design Automation Conference, 1991

Signal analysis and signal transformations for ASIC regular array architecture synthesis.
Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991

Array design methodologies for real-time signal processing in the CATHEDRAL-IV synthesis environment.
Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991

The systematic design of a motion estimation array architecture.
Proceedings of the Application Specific Array Processors, 1991

1990
An integrated automatic design system for complex DSP algorithms.
J. VLSI Signal Process., 1990

Efficient microcoded processor design for fixed rate DFT and FFT.
J. VLSI Signal Process., 1990

Application-specific architectural methodologies for high-throughput digital signal and image processing.
IEEE Trans. Acoust. Speech Signal Process., 1990

Acceleration of relaxation-based circuit simulation using a multiprocessor system.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

An efficient microcode compiler for application specific DSP processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Timing verification using statically sensitizable paths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms.
Proc. IEEE, 1990

Deriving ASIC architectures for the Hough transform.
Parallel Comput., 1990

Testability strategy and test pattern generation for register files and customized memories.
Microprocess. Microsystems, 1990

Efficient VLSI Architectures for a High-Performance Digital Image Communication System.
IEEE J. Sel. Areas Commun., 1990

Cellular automata based self-test for programmable data paths.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Derivation of signal flow direction in MOS VLSI: an alternative.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

DSP specification using the Silage language.
Proceedings of the 1990 International Conference on Acoustics, 1990

CGE: automatic generation of controllers in the CATHEDRAL-II silicon compiler.
Proceedings of the European Design Automation Conference, 1990

Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environment.
Proceedings of the European Design Automation Conference, 1990

SPI: an open interface integrating highly interactive electronic CAD tools.
Proceedings of the European Design Automation Conference, 1990

A combined waveform relaxation: waveform relaxation newton algorithm for efficient parallel circuit simulation.
Proceedings of the European Design Automation Conference, 1990

Open-ended system for high-level synthesis of flexible signal processors.
Proceedings of the European Design Automation Conference, 1990

SLOCOP-II: a versatile timing verification system for MOSVLSI.
Proceedings of the European Design Automation Conference, 1990

A Data Path Layout Assembler for High Performance DSP Circuits.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Extensions to linear mapping for regular arrays with complex processing elements.
Proceedings of the Application Specific Array Processors, 1990

1989
Interprocessor communication in synchronous multiprocessor digital signal processing chips.
IEEE Trans. Acoust. Speech Signal Process., 1989

REDUSA: module generation by automatic elimination of superfluous blocks in regular structures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Description and verification of more-dimensional regular and non-homogeneous structures using a functional hardware description language.
Microprocessing and Microprogramming, 1989

Efficient false path elimination algorithms for timing verification by event graph preprocessing.
Integr., 1989

A testability strategy for multiprocessor architecture.
IEEE Des. Test, 1989

Behavioral Interactive Silicon Compilation for Real Time Synchronous Algorithms.
Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989

Correctness verification of VLSI modules supported by a very efficient Boolean prover.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

Definition and assignment of complex data-paths suited for high throughput applications.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Static Timing Analysis of Dynamically Sensitizable Paths.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Loop Optimization in Register-Transfer Scheduling for DSP-Systems.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
Architectural strategies for an application-specific synchronous multiprocessor environment.
IEEE Trans. Acoust. Speech Signal Process., 1988

SAMURAI: A general and efficient simulated-annealing schedule with fully adaptive annealing parameters.
Integr., 1988

Customized architectural methodologies for high-speed image and video processing.
Proceedings of the IEEE International Conference on Acoustics, 1988

1987
Switch-Electrical Segmented Waveform Relaxation for Digital MOS VLSI and Its Acceleration on Parallel Computers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

Security Considerations in the Design and Implementation of a new DES chip.
Proceedings of the Advances in Cryptology, 1987

1986
Cathedral-II: A Silicon Compiler for Digital Signal Processing.
IEEE Des. Test, 1986

A fast adder-based multiplication unit for customised digital signal processors.
Proceedings of the IEEE International Conference on Acoustics, 1986

An intelligent module generator environment.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985
DIALOG: An Expert Debugging System for MOSVLSI Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985

CAD Tools for the optimized design of custom VLSI wave digital filters.
Proceedings of the IEEE International Conference on Acoustics, 1985

1984
Efficient CAD tools for the coefficient optimisation of arbitrary integrated digital filters.
Proceedings of the IEEE International Conference on Acoustics, 1984

1983
Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983


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