Hsiao-Yun Chiu

According to our database1, Hsiao-Yun Chiu authored at least 2 papers in 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2017
Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed.
IEEE J. Solid State Circuits, 2017


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