Hiroki Koike

According to our database, Hiroki Koike authored at least 21 papers between 1990 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability.

K. Watanabe, T. Shimada, K. Hirose, H. Shindo, D. Kobayashi, Takaho Tanigawa, Shoji Ikeda, Takamitsu Shinada, Hiroki Koike, Tetsuo Endoh, T. Makino, Takeshi Ohshima

Proceedings of the IEEE International Reliability Physics Symposium, 2022

2019

A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications.

Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

IEEE J. Solid State Circuits, 2019

Cyclic groups are CI-groups for balanced configurations.

Hiroki Koike, István Kovács, Dragan Marusic, Mikhail E. Muzychuk

Des. Codes Cryptogr., 2019

A novel memory test system with an electromagnet for STT-MRAM testing.

Ryo Tamura, N. Watanabe, Hiroki Koike, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Soshi Sato

Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019

An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz.

Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018

Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system.

Ryo Tamura, I. Mori, N. Watanabe, Hiroki Koike, Tetsuo Endoh

Proceedings of the Non-Volatile Memory Technology Symposium, 2018

2017

Flag Bicolorings, Pseudo-Orientations, and Double Covers of Maps.

Hiroki Koike, Daniel Pellicer, Miguel Raggi, Steve Wilson

Electron. J. Comb., 2017

2016

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing.

Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno

Proc. IEEE, 2016

An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories.

Tetsuo Endoh, Hiroki Koike, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design.

Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2014

Isomorphic tetravalent cyclic Haar graphs.

Hiroki Koike, István Kovács

Ars Math. Contemp., 2014

2012

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times.

Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

Proceedings of the Symposium on VLSI Circuits, 2012

High-speed simulator including accurate MTJ models for spintronics integrated circuit design.

Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-Wire Serial I/O.

Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura

IEICE Trans. Electron., 2011

2010

An electrically adjustable 3-terminal regulator with post-fabrication level-trimming function.

Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2002

A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers.

Junichi Yamada, Tohru Miwa, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiko Maejima, Hiromitsu Hada, Hidemitsu Mori, Seiichi Takahashi, Hidenori Takeuchi, Takemitsu Kunio

IEEE J. Solid State Circuits, 2002

2001

NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors.

Tohru Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiko Maejima, Hiromitsu Hada, Takemitsu Kunio

IEEE J. Solid State Circuits, 2001

FeRAM device and circuit technologies fully compatible with advanced CMOS.

Hideo Toyoshima, Sota Kobayashi, Junichi Yamada, Tohru Miwa, Hiroki Koike, Hidenori Takeuchi, Hidemitsu Mori, Naoki Kasai, Yukihiko Maejima, Nobuhira Tanabe, Toru Tatsumi, Hiromitsu Hada

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000

NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors.

Tohm Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Tom Tatsumi, Yukihiro Maejima, Hiromitsu Hada, Takemitsu Kunio

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1998

An embedded FeRAM macro cell for a smart card microcontroller.

Tohru Miwa, Junichi Yamada, Yuji Okamoto, Hiroki Koike, Hideo Toyoshiina, Hiromitsu Hada, Yoshihiro Hayashi, Hiroaki Oliizaki, Yoichi Miyasalca, Takemitsu Kunio, Hidenobu Miyamoto, Hideki Gomi, Hiroshi Kitajima

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1990

A BIST scheme using microprogram ROM for large capacity memories.

Hiroki Koike, Toshio Takeshima, Masahide Takada

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990