Hirendu Vaishnav

According to our database, Hirendu Vaishnav authored at least 9 papers between 1993 and 2001.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2001

Alphabetic trees-theory and applications in layout-driven logicsynthesis.

Hirendu Vaishnav, Massoud Pedram

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

1999

Delay-optimal clustering targeting low-power VLSI circuits.

Hirendu Vaishnav, Massoud Pedram

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1997

Power Optimization in VLSI Layout: A Survey.

Massoud Pedram, Hirendu Vaishnav

J. VLSI Signal Process., 1997

Post Layout Speed-up by Event Elimination.

Hirendu Vaishnav, Chi-Keung Lee, Massoud Pedram

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1995

Logic extraction based on normalized netlengths.

Hirendu Vaishnav, Massoud Pedram

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Delay optimal partitioning targeting low power VLSI circuits.

Hirendu Vaishnav, Massoud Pedram

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Minimizing the Routing Cost During Logic Extraction.

Hirendu Vaishnav, Massoud Pedram

Proceedings of the 32st Conference on Design Automation, 1995

1993

PCUBE: A performance driven placement algorithm for low power designs.

Hirendu Vaishnav, Massoud Pedram

Proceedings of the European Design Automation Conference 1993, 1993

Routability-Driven Fanout Optimization.

Hirendu Vaishnav, Massoud Pedram

Proceedings of the 30th Design Automation Conference. Dallas, 1993