Han-Sok Suh
Orcid: 0000-0002-4466-4824
According to our database1,
Han-Sok Suh
authored at least 8 papers
between 2020 and 2024.
Collaborative distances:
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Bibliography
2024
Torch2Chip: An End-to-end Customizable Deep Neural Network Compression and Deployment Toolkit for Prototype Hardware Accelerator Design.
CoRR, 2024
2023
Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA.
ACM Trans. Reconfigurable Technol. Syst., June, 2023
A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity.
IEEE J. Solid State Circuits, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Neuromorph. Comput. Eng., December, 2022
A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2021
2020
FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020