Hailong You

Orcid: 0000-0003-3427-5320

According to our database1, Hailong You authored at least 10 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2024
Semi-Supervised Transfer Learning Framework for Aging-Aware Library Characterization.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

2023
A novel inverted T-shaped negative capacitance TFET for label-free biosensing application.
Microelectron. J., September, 2023

Machine Learning Based Framework for Fast Resource Estimation of RTL Designs Targeting FPGAs.
ACM Trans. Design Autom. Electr. Syst., March, 2023

ASSURER: A PPA-friendly Security Closure Framework for Physical Design.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
High quality hypergraph partitioning for logic emulation.
Integr., 2022

Effective and Efficient Detailed Routing with Adaptive Rip-up Scheme and Pin Access Refinement.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
Placement for Wafer-Scale Deep Learning Accelerator.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2015
Yield-Based Capability Index for Evaluating the Performance of Multivariate Manufacturing Process.
Qual. Reliab. Eng. Int., 2015

2014
A <i>t</i>-chart for Monitoring Multi-variety and Small Batch Production Run.
Qual. Reliab. Eng. Int., 2014

2009
Kriging Model combined with latin hypercube sampling for surrogate modeling of analog integrated circuit performance.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009


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