Guido Bertoni

Orcid: 0000-0002-5122-1589

According to our database1, Guido Bertoni authored at least 65 papers between 2001 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2023
TurboSHAKE.
IACR Cryptol. ePrint Arch., 2023

2018
CASCA: A Design Automation Approach for Designing Hardware Countermeasures Against Side-Channel Attacks.
ACM Trans. Design Autom. Electr. Syst., 2018

Spectral Features of Higher-Order Side-Channel Countermeasures.
IEEE Trans. Computers, 2018

Special Section on Secure Computer Architectures.
IEEE Trans. Computers, 2018

The authenticated encryption schemes Kravatte-SANE and Kravatte-SANSE.
IACR Cryptol. ePrint Arch., 2018

Simulations of Optical Emissions for Attacking AES and Masked AES.
IACR Cryptol. ePrint Arch., 2018

Darth's Saber: A Key Exfiltration Attack for Symmetric Ciphers Using Laser Light.
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018

KangarooTwelve: Fast Hashing Based on Keccak-p.
Proceedings of the Applied Cryptography and Network Security, 2018

2017
Farfalle: parallel permutation-based cryptography.
IACR Trans. Symmetric Cryptol., 2017

A Methodology for the Characterisation of Leakages in Combinatorial Logic.
J. Hardw. Syst. Secur., 2017

Breaking Ed25519 in WolfSSL.
IACR Cryptol. ePrint Arch., 2017

2016
A Fault-Based Secret Key Retrieval Method for ECDSA: Analysis and Countermeasure.
ACM J. Emerg. Technol. Comput. Syst., 2016

A Methodology for the Characterisation of Leakages in Combinatorial Logic.
IACR Cryptol. ePrint Arch., 2016

Farfalle: parallel permutation-based cryptography.
IACR Cryptol. ePrint Arch., 2016

KangarooTwelve: fast hashing based on Keccak-p.
IACR Cryptol. ePrint Arch., 2016

On TLS 1.3 - Early Performance Analysis in the IoT Field.
Proceedings of the 2nd International Conference on Information Systems Security and Privacy, 2016

2015
Keccak.
IACR Cryptol. ePrint Arch., 2015

2014
Introduction to the CHES 2013 special issue.
J. Cryptogr. Eng., 2014

Sufficient conditions for sound tree and sequential hashing modes.
Int. J. Inf. Sec., 2014

The Making of KECCAK.
Cryptologia, 2014

2013
A fault induction technique based on voltage underfeeding with application to attacks against AES and RSA.
J. Syst. Softw., 2013

Sakura: a flexible coding for tree hashing.
IACR Cryptol. ePrint Arch., 2013

Power Analysis of Hardware Implementations Protected with Secret Sharing.
IACR Cryptol. ePrint Arch., 2013

2012
Injection Technologies for Fault Attacks on Microprocessors.
Proceedings of the Fault Analysis in Cryptography, 2012

2011
Duplexing the sponge: single-pass authenticated encryption and other applications.
IACR Cryptol. ePrint Arch., 2011

Fault attack to the elliptic curve digital signature algorithm with multiple bit faults.
Proceedings of the 4th International Conference on Security of Information and Networks, 2011

A novel fault attack against ECDSA.
Proceedings of the HOST 2011, 2011

On the Efficiency of Design Time Evaluation of the Resistance to Power Attacks.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
Low Voltage Fault Attacks to AES and RSA on General Purpose Processors.
IACR Cryptol. ePrint Arch., 2010

Low Voltage Fault Attacks to AES.
Proceedings of the HOST 2010, 2010

Sponge-Based Pseudo-Random Number Generators.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2010

Fault attack on AES with single-bit induced faults.
Proceedings of the Sixth International Conference on Information Assurance and Security, 2010

Secret Key Crypto Implementations.
Proceedings of the Secure Integrated Circuits and Systems, 2010

2009
Practical Power Analysis Attacks to RSA on a Large IP Portfolio SoC.
Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009

Low Voltage Fault Attacks on the RSA Cryptosystem.
Proceedings of the Sixth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2009

The Road from Panama to Keccak via RadioGatún.
Proceedings of the Symmetric Cryptography, 11.01. - 16.01.2009, 2009

Sufficient conditions for sound tree hashing modes.
Proceedings of the Symmetric Cryptography, 11.01. - 16.01.2009, 2009

2008
Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks.
IEEE Trans. Computers, 2008

A pairing SW implementation for Smart-Cards.
J. Syst. Softw., 2008

Parallel Hardware Architectures for the Cryptographic Tate Pairing.
Int. J. Netw. Secur., 2008

A 640 Mbit/S 32-Bit Pipelined Implementation of the AES Algorithm.
Proceedings of the SECRYPT 2008, 2008

A FPGA Coprocessor for the Cryptographic Tate Pairing over Fp.
Proceedings of the Fifth International Conference on Information Technology: New Generations (ITNG 2008), 2008

On the Indifferentiability of the Sponge Construction.
Proceedings of the Advances in Cryptology, 2008

2006
RadioGatún, a belt-and-mill hash function.
IACR Cryptol. ePrint Arch., 2006

Power Aware Design of an Elliptic Curve Coprocessor for 8 bit Platforms.
Proceedings of the 4th IEEE Conference on Pervasive Computing and Communications Workshops (PerCom 2006 Workshops), 2006

ECC Hardware Coprocessors for 8-bit Systems and Power Consumption Considerations.
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006

Performance of HECC Coprocessors Using Inversion-Free Formulae.
Proceedings of the Computational Science and Its Applications, 2006

Software implementation of Tate pairing over GF(2<sup>m</sup>).
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Speeding Up AES By Extending a 32 bit Processor Instruction Set.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
A Parallelized Design for an Elliptic Curve Cryptosystem Coprocessor.
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005

AES Power Attack Based on Induced Cache Miss and Countermeasure.
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005

2004
Efficient and reliable algorithms and architectures for innovative complex cryptographic systems.
PhD thesis, 2004

Finding Optimum Parallel Coprocessor Design for Genus 2 Hyperelliptic Curve Cryptosystems.
IACR Cryptol. ePrint Arch., 2004

Power-efficient ASIC synthesis of cryptographic sboxes.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2003
Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard.
IEEE Trans. Computers, 2003

About the performances of the Advanced Encryption Standard in embedded systems with cache memory.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Systolic and Scalable Architectures for Digit-Serial Multiplication in Fields GF(p<sup>m</sup>).
Proceedings of the Progress in Cryptology, 2003

Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Efficient GF(p<sup>m</sup>) Arithmetic Architectures for Cryptographic Applications.
Proceedings of the Topics in Cryptology, 2003

Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002
A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Efficient Software Implementation of AES on 32-Bit Platforms.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2002

On the Propagation of Faults and Their Detection in a Hardware Implementation of the Advanced Encryption Standard.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2001
Efficient finite field digital-serial multiplier architecture for cryptography applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001


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