Feng Yu

Orcid: 0000-0002-9740-2537

Affiliations:
  • Zhejiang University, College of Biomedical Engineering and Instrument Science, Hangzhou, China
  • Zhejiang University, Department of Instrument Engineering, Hangzhou, China (PhD 2007)


According to our database1, Feng Yu authored at least 43 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
DTP-Net: Learning to Reconstruct EEG Signals in Time-Frequency Domain by Multi-Scale Feature Reuse.
IEEE J. Biomed. Health Informatics, May, 2024

Optimised Serial Commutator FFT Architecture in Terms of Multiplexers.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

2023
General Adaptive Lossless Compression for Multi-Channel Sensor Signals.
IEEE Trans. Circuits Syst. II Express Briefs, December, 2023

2022
Resource Efficient Top-<i>K</i> Sorter on FPGA.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., September, 2022

A Pipelined Algorithm and Area-Efficient Architecture for Serial Real-Valued FFT.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

2021
A Novel Pipelined Algorithm and Modular Architecture for Non-Square Matrix Transposition.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

High-Parallelism Hash-Merge Architecture for Accelerating Join Operation on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020
FPGA-Accelerated Hash Join Operation for Relational Databases.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

High-Throughput Parallel SRAM-Based Hash Join Architecture on FPGA.
IEEE Trans. Circuits Syst., 2020

Modular Pipeline Architecture for Accelerating Join Operation in RDBMS.
IEEE Trans. Circuits Syst., 2020

A Hybrid Pipelined Architecture for High Performance Top-K Sorting on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Multi-Branch Convolutional Neural Network for Automatic Sleep Stage Classification with Embedded Stage Refinement and Residual Attention Channel Fusion.
Sensors, 2020

Learning longer-term dependencies via grouped distributor unit.
Neurocomputing, 2020

Sorting Matrix Architecture for Continuous Data Sequences.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

2019
Resource-Efficient Parallel Tree-Based Join Architecture on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Pipelined Algorithm and Modular Architecture for Matrix Transposition.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Recurrent Highway Networks With Grouped Auxiliary Memory.
IEEE Access, 2019

Fast and Robust Diffusion Kurtosis Parametric Mapping Using a Three-Dimensional Convolutional Neural Network.
IEEE Access, 2019

2018
A Fused Continuous Floating-Point MAC on FPGA.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

2017
A Continuous-Flow Memory-Based Architecture for Real-Valued FFT.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Parameterized L1-Minimization Algorithm for Off-the-Gird Spectral Compressive Sensing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

A Novel Memory-Based Radix-2 Fast Walsh-Hadamard-Fourier Transform Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Modular Serial Pipelined Sorting Architecture for Continuous Variable-Length Sequences with a Very Simple Control Strategy.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Dynamic Parameterized $\ell _{1}$ -Regulation for Single-Snapshot DOA Estimations.
IEEE Commun. Lett., 2017

Off-the-Grid Compressive Time Delay Estimation via Manifold-Based Optimization.
IEEE Commun. Lett., 2017

2016
Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Efficient Circuit for Parallel Bit Reversal.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Time Delay Estimation via Co-Prime Aliased Sparse FFT.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

A novel nonlinear equalizer for extending the dynamic range of analog-to-digital converters.
IEICE Electron. Express, 2016

2015
A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Novel Memory-Based FFT Architecture for Real-Valued Signals Based on a Radix-2 Decimation-In-Frequency Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Pipelined Architecture for a Radix-2 Fast Walsh-Hadamard-Fourier Transform Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Block Region of Interest Method for Real-Time Implementation of Large and Scalable Image Reconstruction.
IEEE Signal Process. Lett., 2015

An Optimum Architecture for Continuous-Flow Parallel Bit Reversal.
IEEE Signal Process. Lett., 2015

A Cloud-Friendly Communication-Optimal Implementation for Strassen's Matrix Multiplication Algorithm.
IEICE Trans. Inf. Syst., 2015

A Combinatorial Aliasing-Based Sparse Fourier Transform.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

2014
Radix-R WHT-FFT with Identical Stage-to-Stage Interconnection Pattern.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Efficient CORDIC-Based Processing Elements in Scalable Complex Matrix Inversion.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

2013
Efficient Utilization of Vector Registers to Improve FFT Performance on SIMD Microprocessors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Block Processor: A resource-distributed architecture.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2013

2012
A Family of Fast Hadamard-Fourier Transform Algorithms.
IEEE Signal Process. Lett., 2012

2011
An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays.
J. Zhejiang Univ. Sci. C, 2011

A pipelined architecture for normal I/O order FFT.
J. Zhejiang Univ. Sci. C, 2011


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