Fan Yang

Affiliations:
  • Avago Technologies, San Jose, CA, USA
  • LSI Corporation, Milpitas, CA, USA (former)
  • University of Iowa, ECE Department, Iowa City, IA, USA (former)


According to our database1, Fan Yang authored at least 10 papers between 2008 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
Silicon Evaluation of Cell-Aware ATPG Tests and Small Delay Tests.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2012
A novel method for fast identification of peak current during test.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Silicon evaluation of faster than at-speed transition delay tests.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

2010
Testing of latch based embedded arrays using scan tests.
Proceedings of the 2011 IEEE International Test Conference, 2010

2009
Improving the Detectability of Resistive Open Faults in Scan Cells.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Detectability of internal bridging faults in scan chains.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
On the Detectability of Scan Chain Internal Faults - An Industrial Case Study.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Detection of Internal Stuck-open Faults in Scan Chains.
Proceedings of the 2008 IEEE International Test Conference, 2008

An Enhanced Logic BIST Architecture for Online Testing.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008


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