Dongsuk Jeon
Orcid: 0000-0002-0395-8076
According to our database1,
Dongsuk Jeon
authored at least 55 papers
between 2011 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
DropBP: Accelerating Fine-Tuning of Large Language Models by Dropping Backward Propagation.
CoRR, 2024
A 28nm All-Digital Droop Detection and Mitigation Circuit Using a Shared Dual-Mode Delay Line with 14.8% VminReduction and 42.9% Throughput Gain.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
A 28nm 157TOPS/W 446.9Kb/mm<sup>2</sup> Compute-In-Memory SRAM Macro with Analog-Digital Hybrid Computing for Deep Neural Network Inference.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A 65 nm 12.92-nJ/Inference Mixed-Signal Neuromorphic Processor for Image Classification.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
A Real-Time Object Detection Processor With xnor-Based Variable-Precision Computing Unit.
IEEE Trans. Very Large Scale Integr. Syst., June, 2023
Curriculum Reinforcement Learning From Avoiding Collisions to Navigating Among Movable Obstacles in Diverse Environments.
IEEE Robotics Autom. Lett., May, 2023
A0.81 mm<sup>2</sup> 740μW Real-Time Speech Enhancement Processor Using Multiplier-Less PE Arrays for Hearing Aids in 28nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the Eleventh International Conference on Learning Representations, 2023
A 4.27TFLOPS/W FP4/FP8 Hybrid-Precision Neural Network Training Processor Using Shift-Add MAC and Reconfigurable PE Array.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
A 270-mA Self-Calibrating-Clocked Output-Capacitor-Free LDO With 0.15-1.15V Output Range and 0.183-fs FoM.
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees.
IEEE J. Solid State Circuits, 2022
Toward Efficient Low-Precision Training: Data Format Optimization and Hysteresis Quantization.
Proceedings of the Tenth International Conference on Learning Representations, 2022
A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
A low power neural network training processor with 8-bit floating point with a shared exponent bias and fused multiply add trees.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
A 65nm 0.6-1.2V Low-Dropout Regulator Using Voltage-Difference-to-Time Converter With Direct Output Feedback.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A Multi-Channel Spike Sorting Processor With Accurate Clustering Algorithm Using Convolutional Autoencoder.
IEEE Trans. Biomed. Circuits Syst., 2021
Activation Sharing with Asymmetric Paths Solves Weight Transport Problem without Bidirectional Connection.
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021
A 40nm 4.81TFLOPS/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add Tree.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the IEEE International Conference on Acoustics, 2021
2020
A 65-nm Neuromorphic Image Classification Processor With Energy-Efficient Training Through Direct Spike-Only Feedback.
IEEE J. Solid State Circuits, 2020
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175µW/Channel in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Comput. Archit. Lett., 2019
Microarchitecture-Aware Code Generation for Deep Learning on Single-ISA Heterogeneous Multi-Core Mobile Processors.
IEEE Access, 2019
A 65nm 236.5nJ/Classification Neuromorphic Processor with 7.5% Energy Overhead On-Chip Learning Using Direct Spike-Only Feedback.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector.
IEEE J. Solid State Circuits, 2018
2017
IEEE J. Solid State Circuits, 2017
8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm<sup>2</sup> per channel in 65-nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
24.1 A 0.6V 8mW 3D vision processor for a navigation device for the visually impaired.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the International SoC Design Conference, 2016
Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm<sup>2</sup> per Channel in 65-nm CMOS.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
IEEE J. Solid State Circuits, 2015
A 120nW 8b sub-ranging SAR ADC with signal-dependent charge recycling for biomedical applications.
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
2014
An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS.
IEEE J. Solid State Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
IEEE J. Solid State Circuits, 2012
Extending energy-saving voltage scaling in ultra low voltage integrated circuit designs.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the IEEE International Conference on Acoustics, 2011
Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design.
Proceedings of the 48th Design Automation Conference, 2011