Dongbing Fu

According to our database1, Dongbing Fu authored at least 7 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A low power 16-bit 50 MS/s pipeline ADC with 104 dB SFDR in 0.18 μm CMOS.
Microelectron. J., 2024

A 3.3V 14-bit 125MS/s pipeline ADC with hybrid 1.8V/3.3V MOSFET technique in 0.18µm CMOS.
IEICE Electron. Express, 2024

2021
A Low-Area and Low-Power Comma Detection and Word Alignment Circuits for JESD204B/C Controller.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020
A 5-13.5 Gb/s Multistandard Receiver With High Jitter Tolerance Digital CDR in 40-nm CMOS Process.
IEEE Trans. Circuits Syst., 2020

2019
A High Speed Clock Receiver for DAC with Cross point and Duty Cycle Adjustable Capability.
Proceedings of the ICITEE-2019: 2nd International Conference on Information Technologies and Electrical Engineering, 2019

2018
A high efficient CTLE for 12.5 Gbps receiver of JESD204B standard.
IEICE Electron. Express, 2018

2013
A high-speed front-end circuit used in a 16bit 250MSPS pipelined ADC.
Proceedings of the IEEE 10th International Conference on ASIC, 2013


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