Dong Wang

Orcid: 0000-0002-0068-8824

Affiliations:
  • Beijing Jiaotong University, Institute of Information Science, Beijing Key Laboratory of Advanced Information Science and Network Technology, China
  • Tsinghua University, Institute of Microelectronics, Beijing, China (2010 - 2013)
  • Xi'an Jiaotong University, China (PhD 2010)


According to our database1, Dong Wang authored at least 42 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
End-to-end acceleration of the YOLO object detection framework on FPGA-only devices.
Neural Comput. Appl., January, 2024

Ulit-BiDet: An Ultralightweight Object Detector for SAR Images Based on Binary Neural Networks.
IEEE Trans. Geosci. Remote. Sens., 2024

2023
ABM-SpConv-SIMD: Accelerating Convolutional Neural Network Inference for Industrial IoT Applications on Edge Devices.
IEEE Trans. Netw. Sci. Eng., 2023

2022
TA-BiDet: Task-aligned binary object detector.
Neurocomputing, 2022

An OpenCL-Based FPGA Accelerator for Faster R-CNN.
Entropy, 2022

MultiQuant: Training Once for Multi-bit Quantization of Neural Networks.
Proceedings of the Thirty-First International Joint Conference on Artificial Intelligence, 2022

2021
Fast and Accurate Object Detection in Remote Sensing Images Based on Lightweight Deep Neural Network.
Sensors, 2021

A dedicated hardware accelerator for real-time acceleration of YOLOv2.
J. Real Time Image Process., 2021

GenExp: Multi-objective pruning for deep neural network based on genetic algorithm.
Neurocomputing, 2021

Edge-Wise One-Level Global Pruning on NAS Generated Networks.
Proceedings of the Pattern Recognition and Computer Vision - 4th Chinese Conference, 2021

2020
DSP-Efficient Hardware Acceleration of Convolutional Neural Network Inference on FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

An FPGA-Based Hardware Accelerator for Real-Time Block-Matching and 3D Filtering.
IEEE Access, 2020

Sparse-YOLO: Hardware/Software Co-Design of an FPGA Accelerator for YOLOv2.
IEEE Access, 2020

2019
Training Low Bitwidth Model with Weight Normalization for Convolutional Neural Networks.
Proceedings of the Pattern Recognition and Computer Vision - Second Chinese Conference, 2019

A Scalable OpenCL-Based FPGA Accelerator for YOLOv2.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

ABM-SpConv: A Novel Approach to FPGA-Based Acceleration of Convolutional Neural Network Inference.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
A Scalable FPGA Accelerator for Convolutional Neural Networks.
Proceedings of the Advanced Computer Architecture - 12th Conference, 2018

2017
Performance Analysis of a RTS/CTS-Based Channel Accessing Mechanism for MU-MIMO WLANs.
Wirel. Pers. Commun., 2017

PipeCNN: An OpenCL-based open-source FPGA accelerator for convolution neural networks.
Proceedings of the International Conference on Field Programmable Technology, 2017

2016
An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform.
IEICE Trans. Inf. Syst., 2016

PipeCNN: An OpenCL-Based FPGA Accelerator for Large-Scale Convolution Neuron Networks.
CoRR, 2016

2015
Correction to "An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding".
IEEE Trans. Multim., 2015

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding.
IEEE Trans. Multim., 2015

A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014
SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration.
IEEE Trans. Very Large Scale Integr. Syst., 2014

(M, p, k)-Friendly Points: A Table-Based Method to Evaluate Trigonometric Function.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Complex Function Approximation Using Two-Dimensional Interpolation.
IEEE Trans. Computers, 2014

Reduced-error constant correction truncated multiplier.
IEICE Electron. Express, 2014

A parallel arithmetic array for accelerating compute-intensive applications.
IEICE Electron. Express, 2014

Implementation of multi-standard video decoder on a heterogeneous coarse-grained reconfigurable processor.
Sci. China Inf. Sci., 2014

The diffserv cognitive network node with Controlled-UDP.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A novel secure MIMO cognitive network.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Security Spectrum Auction Framework for Cognitive Radio Networks.
J. Comput., 2013

A high-throughput fixed-point complex divider for FPGAs.
IEICE Electron. Express, 2013

ReSSIM: a mixed-level simulator for dynamic coarse-grained reconfigurable processor.
Sci. China Inf. Sci., 2013

Battery-Aware MAC Analytical Modeling for Extending Lifetime of Low Duty-Cycled Wireless Sensor Network.
Proceedings of the IEEE Eighth International Conference on Networking, 2013

Implementation of multi-standard video decoding algorithms on a coarse-grained reconfigurable multimedia processor.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A Radix-16 Combined Complex Division/Square Root Unit with Operand Prescaling.
IEEE Trans. Computers, 2012

2010
Design of High-Throughput Fixed-Point Complex Reciprocal/Square-Root Unit.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

2009
A radix-8 complex divider for FPGA implementation.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
An Efficient Motion Adaptive De-interlacing and Its VLSI Architecture Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008


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