Debbie Marr

According to our database1, Debbie Marr authored at least 22 papers between 2015 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
SE1: What Technologies Will Shape the Future of Computing?
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2019
Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018
Guest Editors' Introduction: Hardware Accelerators for Data Centers.
IEEE Des. Test, 2018

WRPN & Apprentice: Methods for Training and Inference using Low-Precision Numerics.
CoRR, 2018

WRPN: Wide Reduced-Precision Networks.
Proceedings of the 6th International Conference on Learning Representations, 2018

Apprentice: Using Knowledge Distillation Techniques To Improve Low-Precision Network Accuracy.
Proceedings of the 6th International Conference on Learning Representations, 2018

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017
Low Precision RNNs: Quantizing RNNs Without Losing Accuracy.
CoRR, 2017

WRPN: Training and Inference using Wide Reduced-Precision Networks.
CoRR, 2017

Accelerating Deep Convolutional Networks using low-precision and sparsity.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

Customizable FPGA OpenCL matrix multiply design template for deep neural networks.
Proceedings of the International Conference on Field Programmable Technology, 2017

High performance binary neural networks on the Xeon+FPGA™ platform.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Fine-grained accelerators for sparse machine learning workloads.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Efficient Execution of Bursty Applications.
IEEE Comput. Archit. Lett., 2016

Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Hardware accelerator for analytics of sparse data.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
A sparse matrix vector multiply accelerator for support vector machine.
Proceedings of the 2015 International Conference on Compilers, 2015


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