Damu Radhakrishnan

According to our database, Damu Radhakrishnan authored at least 18 papers between 1985 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2009

Redundant binary partial product generators for compact accumulation in Booth multipliers.

Bijoy Antony Jose, Damu Radhakrishnan

Microelectron. J., 2009

2008

Delay Efficient 32-Bit Carry-Skip Adder.

Yu Shen Lin, Damu Radhakrishnan

VLSI Design, 2008

2006

Delay Optimized Redundant Binary Adders.

Bijoy Antony Jose, Damu Radhakrishnan

Proceedings of the 13th IEEE International Conference on Electronics, 2006

2004

Shift Invert Coding (SINV) for Low Power VLSI.

Jayapreetha Natesan, Damu Radhakrishnan

Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

A Low Energy Deep Sub-Micron Bus Coding Technique.

Naveen K. Samala, Damu Radhakrishnan, Baback A. Izadi

Proceedings of the International Conference on Embedded Systems and Applications, 2004

A Novel Bus Encoding Technique for Low Power VLSI.

Jayapreetha Natesan, Damu Radhakrishnan

Proceedings of the International Conference on Embedded Systems and Applications, 2004

Switching Activity Minimization in Combinational Logic Design.

Rakesh Menon, Sarita Chennupati, Naveen K. Samala, Damu Radhakrishnan, Baback A. Izadi

Proceedings of the International Conference on Embedded Systems and Applications, 2004

A Low-Power Pipelined Implementation of 2D Discrete Wavelet Transform.

Yong Liu, Edmund Ming-Kit Lai, A. Benjamin Premkumar, Damu Radhakrishnan

Proceedings of the International Conference on Embedded Systems and Applications, 2004

Experimental Analysis of Batteries Under Continuous and Intermittent Operations.

Smith Castillo, Naveen K. Samala, Kerron Manwaring, Baback A. Izadi, Damu Radhakrishnan

Proceedings of the International Conference on Embedded Systems and Applications, 2004

2003

Low-Power Dynamic Scheduling in Heterogeneous Systems.

Saumya Uppaluri, Baback A. Izadi, Damu Radhakrishnan

Proceedings of the International Conference on Embedded Systems and Applications, 2003

Power Optimized Combinational Logic Design.

Rakesh Menon, Sarita Chennupati, Naveen K. Samala, Damu Radhakrishnan, Baback A. Izadi

Proceedings of the International Conference on Embedded Systems and Applications, 2003

2001

Fault-tolerance scheme for an RNS MAC: performance and cost analysis.

Adimathara P. Preethy, Damu Radhakrishnan, Amos Omondi

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A high performance RNS multiply-accumulate unit.

Adimathara P. Preethy, Damu Radhakrishnan, Amos Omondi

Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

2000

Pass logic circuits with reduced switching activity for low power DSP processors.

Damu Radhakrishnan

Proceedings of the IEEE International Conference on Acoustics, 2000

1999

A Parallel Approach to Direct Analog-to-Residue Conversion.

Damu Radhakrishnan, Adimathara P. Preethy

Inf. Process. Lett., 1999

1998

A new approach to data conversion: direct analog-to-residue converter.

Damu Radhakrishnan, Adimathara P. Preethy

Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

1990

Fault tolerance in RNS: an efficient approach.

Damu Radhakrishnan, Taejin Pyon

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1985

Multiple Output Pass Networks: Design and Testing.

Ali Feizi, Damu Radhakrishnan

Proceedings of the Proceedings International Test Conference 1985, 1985