Christoph Roth

According to our database1, Christoph Roth authored at least 33 papers between 2008 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2015
Adaptive algorithm and tool flow for accelerating SystemC on many-core architectures.
Microprocess. Microsystems, 2015

An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity.
IEEE J. Solid State Circuits, 2015

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Parallele und kooperative Simulation für eingebettete Multiprozessorsysteme.
PhD thesis, 2014

Efficient Parallel Turbo-Decoding for High-Throughput Wireless Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Power-efficient turbo-decoder design based on algorithm-specific power domain partitioning.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

An evolved EDGE PHY ASIC supporting soft-output equalization and Rx diversity.
Proceedings of the ESSCIRC 2014, 2014

Adaptive Algorithm and Tool Flow for Accelerating System C on Many-Core Architectures.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Statistical data correction for unreliable memories.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
A SystemC modeling and simulation methodology for fast and accurate parallel MPSoC simulation.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Improving parallel MPSoC simulation performance by exploiting dynamic routing delay prediction.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

Addiguration: Exploring configuration behavior of Spartan-3 devices.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

A parallelized layered QC-LDPC decoder for IEEE 802.11ad.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Development and Evaluation of Distributed Simulation of Embedded Systems Using Ptolemy and HLA.
Proceedings of the 17th IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications, 2013

2012
Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels.
Int. J. Reconfigurable Comput., 2012

Turbo decoder design for high code rates.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

A Framework for exploration of parallel SystemC simulation on the single-chip cloud computer.
Proceedings of the International ICST Conference on Simulation Tools and Techniques, 2012

A novel constrained-Viterbi algorithm with linear equalization and grouping assistance.
Proceedings of the 2012 International Symposium on Wireless Communication Systems (ISWCS), 2012

Asynchronous parallel MPSoC simulation on the Single-Chip Cloud Computer.
Proceedings of the 2012 International Symposium on System on Chip, 2012

On the exploitation of the inherent error resilience of wireless systems under unreliable silicon.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Data mapping for unreliable memories.
Proceedings of the 50th Annual Allerton Conference on Communication, 2012

2011
HLA-based simulation environment for distributed SystemC simulation.
Proceedings of the 4th International ICST Conference on Simulation Tools and Techniques, 2011

Flexible and efficient co-simulation of networked embedded devices.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

An approach for power and performance evaluation of reconfigurable SoC at mixed abstraction levels.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

The Study of a Dynamic Reconfiguration Manager for Systems-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Modular Framework for Multi-level Multi-device MPSoC Simulation.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2010
V2X Simulation Environment for Comprehensive Design Space Exploration Verification and Test.
Proceedings of the Joint Workshop of the German Research Training Groups in Computer Science, 2010

2009
System concept for an FPGA based real-time capable automotive ECU simulation system.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Testing of an FPGA Based C2X-Communication Prototype with a Model Based Traffic Generation.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

Design of a Vehicle-to-Vehicle communication system on reconfigurable hardware.
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

Priority-based packet communication on a bus-shaped structure for FPGA-systems.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Configurable high-throughput decoder architecture for quasi-cyclic LDPC codes.
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008


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