Chia-Lin Yang

According to our database, Chia-Lin Yang authored at least 116 papers between 1998 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Impact of Non-Volatile Memory Cells on Spiking Neural Network Annealing Machine With In-Situ Synapse Processing.

Ming-Liang Wei, Mikail Yayla, Shu-Yin Ho, Jian-Jia Chen, Hussam Amrouch, Chia-Lin Yang

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023

Understanding Computer Architecture Sustainability.

Chia-Lin Yang

Computer, September, 2023

HW/SW Codesign for Robust and Efficient Binarized SNNs by Capacitor Minimization.

Mikail Yayla, Simon Thomann, Ming-Liang Wei, Chia-Lin Yang, Jian-Jia Chen, Hussam Amrouch

CoRR, 2023

Reliable Brain-inspired AI Accelerators using Classical and Emerging Memories.

Mikail Yayla, Simon Thomann, Md. Mazharul Islam, Ming-Liang Wei, Shu-Yin Ho, Ahmedullah Aziz, Chia-Lin Yang, Jian-Jia Chen, Hussam Amrouch

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Tensor Movement Orchestration in Multi-GPU Training Systems.

Shao-Fu Lin, Yi-Jung Chen, Hsiang-Yun Cheng, Chia-Lin Yang

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Unified Agile Accuracy Assessment in Computing-in-Memory Neural Accelerators by Layerwise Dynamical Isometry.

Xuan-Jun Chen, Cynthia Kuan, Chia-Lin Yang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications.

Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jerónimo Castrillón, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng

Proceedings of the International Conference on Compilers, 2023

2022

DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators.

Wei-Ting Lin, Hsiang-Yun Cheng, Chia-Lin Yang, Meng-Yao Lin, Kai Lien, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang, Yen-Ting Tsou, Chin-Fu Nien

ACM Trans. Embed. Comput. Syst., 2022

A Forward Speculative Interference Attack.

Chia-Lin Yang

Computer, 2022

Efficient and Atomic-Durable Persistent Memory through In-PM Hybrid Logging.

Nai-Jia Dong, Hsiang-Yun Cheng, Chia-Lin Yang, Bo-Rong Lin, Hsiang-Pang Li

Proceedings of the 11th IEEE Non-Volatile Memory Systems and Applications Symposium, 2022

Efficient Bad Block Management with Cluster Similarity.

Jui-Nan Yen, Yao-Ching Hsieh, Cheng-Yu Chen, Tseng-Yi Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Yixin Luo

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

RM-SSD: In-Storage Computing for Large-Scale Recommendation Inference.

Xuan Sun, Hu Wan, Qiao Li, Chia-Lin Yang, Tei-Wei Kuo, Chun Jason Xue

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator.

Yen-Ting Tsou, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Jian-Jia Chen, Der-Yu Tsai

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support.

Chung-Hsiang Lin, Shao-Fu Lin, Yi-Jung Chen, En-Yu Jenp, Chia-Lin Yang

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

ezGeno: an automatic model selection package for genomic data analysis.

Jun-Liang Lin, Tsung-Ting Hsieh, Yi-An Tung, Xuan-Jun Chen, Yu-Chun Hsiao, Chia-Lin Yang, Tyng-Luh Liu, Chien-Yu Chen

Bioinform., 2021

Analyzing the Interplay Between Random Shuffling and Storage Devices for Efficient Machine Learning.

Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang, Han-Wei Huang

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

A Dense Tensor Accelerator with Data Exchange Mesh for DNN and Vision Workloads.

Yu-Sheng Lin, Wei-Chao Chen, Chia-Lin Yang, Shao-Yi Chien

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Robust Brain-Inspired Computing: On the Reliability of Spiking Neural Network Using Emerging Non-Volatile Synapses.

Ming-Liang Wei, Hussam Amrouch, Cheng-Lin Sung, Hang-Ting Lue, Chia-Lin Yang, Keh-Chung Wang, Chih-Yuan Lu

Proceedings of the IEEE International Reliability Physics Symposium, 2021

Binarized SNNs: Efficient and Error-Resilient Spiking Neural Networks through Binarization.

Ming-Liang Wei, Mikail Yayla, Shu-Yin Ho, Jian-Jia Chen, Chia-Lin Yang, Hussam Amrouch

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Future Computing Platform Design: A Cross-Layer Design Approach.

Hsiang-Yun Cheng, Chun-Feng Wu, Christian Hakert, Kuan-Hsun Chen, Yuan-Hao Chang, Jian-Jia Chen, Chia-Lin Yang, Tei-Wei Kuo

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

FlashEmbedding: storing embedding tables in SSD for large-scale recommender systems.

Hu Wan, Xuan Sun, Yufei Cui, Chia-Lin Yang, Tei-Wei Kuo, Chun Jason Xue

Proceedings of the APSys '21: 12th ACM SIGOPS Asia-Pacific Workshop on Systems, 2021

2020

Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks.

Qilin Zheng, Zongwei Wang, Zishun Feng, Bonan Yan, Yimao Cai, Ru Huang, Yiran Chen, Chia-Lin Yang, Hai Helen Li

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Fair Down to the Device: A GC-Aware Fair Scheduler for SSD.

Cheng Ji, Lun Wang, Qiao Li, Congming Gao, Liang Shi, Chia-Lin Yang, Chun Jason Xue

Proceedings of the 2019 IEEE Non-Volatile Memory Systems and Applications Symposium, 2019

Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks.

Tzu-Hsien Yang, Hsiang-Yun Cheng, Chia-Lin Yang, I-Ching Tseng, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li

Proceedings of the 46th International Symposium on Computer Architecture, 2019

Iotbench: A Benchmark Suite for Intelligent Internet of Things Edge Devices.

Chien-I Lee, Meng-Yao Lin, Chia-Lin Yang, Yen-Kuang Chen

Proceedings of the 2019 IEEE International Conference on Image Processing, 2019

The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper.

Jörg Henkel, Hussam Amrouch, Martin Rapp, Sami Salamin, Dayane Reis, Di Gao, Xunzhao Yin, Michael T. Niemier, Cheng Zhuo, Xiaobo Sharon Hu, Hsiang-Yun Cheng, Chia-Lin Yang

Proceedings of the International Conference on Computer-Aided Design, 2019

2018

LIRS: Enabling efficient machine learning on NVM-based storage via a lightweight implementation of random shuffling.

Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang

CoRR, 2018

DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning.

Meng-Yao Lin, Hsiang-Yun Cheng, Wei-Ting Lin, Tzu-Hsien Yang, I-Ching Tseng, Chia-Lin Yang, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang

Proceedings of the International Conference on Computer-Aided Design, 2018

Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures.

Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration.

Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang

ACM Trans. Design Autom. Electr. Syst., 2017

Exploiting Write Heterogeneity of Morphable MLC/SLC SSDs in Datacenters with Service-Level Objectives.

Che-Wei Chang, Geng-You Chen, Yi-Jung Chen, Chia-Wei Yeh, Pei Yin Eng, Ana Cheung, Chia-Lin Yang

IEEE Trans. Computers, 2017

Recap of the 2017 International Symposium on Low Power Electronics and Design (ISLPED).

David Garrett, Chia-Lin Yang

IEEE Des. Test, 2017

Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling.

Li-Jhan Chen, Hsiang-Yun Cheng, Po-Han Wang, Chia-Lin Yang

IEEE Comput. Archit. Lett., 2017

Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator.

Li Wang, Ren-Wei Tsai, Shao-Chung Wang, Kun-Chih Chen, Po-Han Wang, Hsiang-Yun Cheng, Yi-Chung Lee, Sheng-Jie Shu, Chun-Chieh Yang, Min-Yih Hsu, Li-Chen Kan, Chao-Lin Lee, Tzu-Chieh Yu, Rih-Ding Peng, Chia-Lin Yang, Yuan-Shin Hwang, Jenq Kuen Lee, Shiao-Li Tsao, Ming Ouhyoung

Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

Message from the general co-chairs.

David Garrett, Chia-Lin Yang

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach.

Chun-Hao Lai, Jishen Zhao, Chia-Lin Yang

Proceedings of the 54th Annual Design Automation Conference, 2017

Enabling fast preemption via Dual-Kernel support on GPUs.

Li-Wei Shieh, Kun-Chih Chen, Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality.

Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li

IEEE Trans. Computers, 2016

Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture.

Po-Han Wang, Cheng-Hsuan Li, Chia-Lin Yang

Proceedings of the 53rd Annual Design Automation Conference, 2016

MCSSim: A memory channel storage simulator.

Renhai Chen, Zili Shao, Chia-Lin Yang, Tao Li

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

System-Level Performance and Power Optimization for MPSoC: A Memory Access-Aware Approach.

Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Tay-Jyi Lin, Chih-Wen Hsueh, Naehyuck Chang

ACM Trans. Embed. Comput. Syst., 2015

SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs.

Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang

ACM Trans. Archit. Code Optim., 2015

Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs.

Yi-Jung Chen, Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu

Proceedings of the 2015 Conference on research in adaptive and convergent systems, 2015

A buffer cache architecture for smartphones with hybrid DRAM/PCM memory.

Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang

Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

Improving DRAM latency with dynamic asymmetric subarray.

Shih-Lien Lu, Ying-Chen Lin, Chia-Lin Yang

Proceedings of the 48th International Symposium on Microarchitecture, 2015

Fine-grained write scheduling for PCM performance improvement under write power budget.

Chun-Hao Lai, Shun-Chih Yu, Chia-Lin Yang, Hsiang-Pang Li

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2014

Guest Editors' Introduction: Cloud Computing for Embedded Systems.

Martin Dimitrov, Yung-Hsiang Lu, Chia-Lin Yang

IEEE Des. Test, 2014

Full system simulation framework for integrated CPU/GPU architecture.

Po-Han Wang, Gen-Hong Liu, Jen-Chieh Yeh, Tse-Min Chen, Hsu-Yao Huang, Chia-Lin Yang, Shih-Lien Liu, James Greensky

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs.

Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

NVM duet: unified working memory and persistent store architecture.

Ren-Shuo Liu, De-Yu Shen, Chia-Lin Yang, Shun-Chih Yu, Cheng-Yuan Michael Wang

Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

2013

Thermal coupling aware task migration using neighboring core search for many-core systems.

Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs.

Ping-Sheng Lin, Yi-Jung Chen, Chia-Lin Yang, Yi-Chang Lu

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

DuraCache: a durable SSD cache using MLC NAND flash.

Ren-Shuo Liu, Chia-Lin Yang, Cheng-Hsuan Li, Geng-You Chen

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

A cycle-level SIMT-GPU simulation framework.

Po-Han Wang, Chien-Wei Lo, Chia-Lin Yang, Yu-Jung Cheng

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012

SECRET: Selective error correction for refresh energy reduction in DRAMs.

Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs.

Yi-Jung Chen, Chia-Lin Yang, Jian-Jia Chen

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Optimizing NAND flash-based SSDs via retention relaxation.

Ren-Shuo Liu, Chia-Lin Yang, Wei Wu

Proceedings of the 10th USENIX conference on File and Storage Technologies, 2012

Age-based PCM wear leveling with nearly zero search cost.

Chi-Hao Chen, Pi-Cheng Hsiu, Tei-Wei Kuo, Chia-Lin Yang, Cheng-Yuan Michael Wang

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Memory access aware power gating for MPSoCs.

Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Naehyuck Chang

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling.

Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems.

Yi-Jung Chen, Chia-Lin Yang, Jaw-Wei Chi, Jian-Jia Chen

IEEE Trans. Computers, 2011

Power gating strategies on GPUs.

Po-Han Wang, Chia-Lin Yang, Yen-Ming Chen, Yu-Jung Cheng

ACM Trans. Archit. Code Optim., 2011

A Study of a Heuristic Capacity Planning Algorithm for Weapon Production System.

James C. Chen, Kou-Huang Chen, Chien-Hsin Lin, Chia-Wen Chen, Chia-Lin Yang

Int. J. Electron. Bus. Manag., 2011

A SAT-based routing algorithm for cross-referencing biochips.

Ping-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho, Chia-Lin Yang, Yao-Wen Chang

Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

2010

Memory Latency Reduction via Thread Throttling.

Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Dynamic thermal management for networked embedded systems under harsh ambient temperature variation.

Sangyoung Park, Jian-Jia Chen, Donghwa Shin, Younghyun Kim, Chia-Lin Yang, Naehyuck Chang

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Parallelization and characterization of GARCH option pricing on GPUs.

Ren-Shuo Liu, Yun-Cheng Tsai, Chia-Lin Yang

Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010

Hierarchical memory scheduling for multimedia MPSoCs.

Ye-Jyun Lin, Chia-Lin Yang, Tay-Jyi Lin, Jiao-Wei Huang, Naehyuck Chang

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

PM-COSYN: PE and memory co-synthesis for MPSoCs.

Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang

Proceedings of the Design, Automation and Test in Europe, 2010

2009

A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters.

Sung-Wen Wang, Shu-Sian Yang, Hong-Ming Chen, Chia-Lin Yang, Ja-Ling Wu

J. Signal Process. Syst., 2009

Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs.

Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin

ACM Trans. Design Autom. Electr. Syst., 2009

T-trees: A tree-based representation for temporal and three-dimensional floorplanning.

Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang

ACM Trans. Design Autom. Electr. Syst., 2009

A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips.

Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

An architectural co-synthesis algorithm for energy-aware Network-on-Chip design.

Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang

J. Syst. Archit., 2009

A Predictive Shutdown Technique for GPU Shader Processors.

Po-Han Wang, Yen-Ming Chen, Chia-Lin Yang, Yu-Jung Cheng

IEEE Comput. Archit. Lett., 2009

PPT: joint performance/power/thermal management of DRAM memory for multi-core systems.

Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Thermal modeling for 3D-ICs with integrated microchannel cooling.

Hitoshi Mizunuma, Chia-Lin Yang, Yi-Chang Lu

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008

Energy-Aware Flash Memory Management in Virtual Memory System.

Han-Lin Li, Chia-Lin Yang, Hung-Wei Tseng

IEEE Trans. Very Large Scale Integr. Syst., 2008

BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips.

Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs.

Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A progressive-ILP based routing algorithm for cross-referencing biochips.

Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang

Proceedings of the 45th Design Automation Conference, 2008

2007

Temporal floorplanning using the three-dimensional transitive closure subGraph.

Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang

ACM Trans. Design Autom. Electr. Syst., 2007

Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation.

Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang

ACM J. Emerg. Technol. Comput. Syst., 2007

An architectural co-synthesis algorithm for energy-aware network-on-chip design.

Wei-Hsuan Hung, Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang, Alan P. Su

Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), 2007

Efficient obstacle-avoiding rectilinear steiner tree construction.

Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang

Proceedings of the 2007 International Symposium on Physical Design, 2007

Post-placement leakage optimization for partially dynamically reconfigurable FPGAs.

Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design.

Shao-Yi Chien, Chi-Sheng Shih, Mong-Kai Ku, Chia-Lin Yang, Yao-Wen Chang, Tei-Wei Kuo, Liang-Gee Chen

Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

BioRoute: a network-flow based routing algorithm for digital microfluidic biochips.

Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Energy-efficient real-time task scheduling with task rejection.

Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang, Ku-Jei King

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Cache leakage control mechanism for hard real-time systems.

Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen

Proceedings of the 2007 International Conference on Compilers, 2007

2006

A Space-Efficient Caching Mechanism for Flash-Memory Address Translation.

Chin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang

Proceedings of the Ninth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2006), 2006

An energy-efficient virtual memory system with flash memory as the secondary storage.

Hung-Wei Tseng, Han-Lin Li, Chia-Lin Yang

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Hierarchical value cache encoding for off-chip data bus.

Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Placement of digital microfluidic biochips using the t-tree formulation.

Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang

Proceedings of the 43rd Design Automation Conference, 2006

Branch Behavior Characterization for Multimedia Applications.

Chia-Lin Yang, Shun-Ying Wang, Yi-Jung Chen

Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2005

Software-Controlled Cache Architecture for Energy Efficiency.

Chia-Lin Yang, Hong-Wei Tseng, Chia-Chiang Ho, Ja-Ling Wu

IEEE Trans. Circuits Syst. Video Technol., 2005

Reconfigurable Platform for Content Science Research.

Chi-Sheng Shih, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen

Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 2005

Joint exploration of architectural and physical design spaces with thermal consideration.

Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Cache Leakage Management for Multi-programming Workloads.

Chun-Yang Chen, Chia-Lin Yang, Shih-Hao Hung

Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004

Zero-aware asymmetric SRAM cell for reducing cache power in writing zero.

Yen-Jen Chang, Feipei Lai, Chia-Lin Yang

IEEE Trans. Very Large Scale Integr. Syst., 2004

Tolerating memory latency through push prefetching for pointer-intensive applications.

Chia-Lin Yang, Alvin R. Lebeck, Hung-Wei Tseng, Chien-Hao Lee

ACM Trans. Archit. Code Optim., 2004

Profit-driven uniprocessor scheduling with energy and timing constraints.

Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang

Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004

Workload Characterization of the H.264/AVC Decoder.

Tse-Tsung Shih, Chia-Lin Yang, Yi-Shin Tung

Proceedings of the Advances in Multimedia Information Processing - PCM 2004, 5th Pacific Rim Conference on Multimedia, Tokyo, Japan, November 30, 2004

HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction.

Chia-Lin Yang, Chien-Hao Lee

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Temporal floorplanning using the T-tree formulation.

Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations.

Jian-Jia Chen, Heng-Ruey Hsu, Kai-Hsiang Chuang, Chia-Lin Yang, Ai-Chun Pang, Tei-Wei Kuo

Proceedings of the 16th Euromicro Conference on Real-Time Systems (ECRTS 2004), 30 June, 2004

Value-Conscious Cache: Simple Technique for Reducing Cache Access Power.

Yen-Jen Chang, Chia-Lin Yang, Feipei Lai

Proceedings of the 2004 Design, 2004

Energy-efficient flash-memory storage systems with an interrupt-emulation mechanism.

Chin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Temporal floorplanning using 3D-subTCG.

Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

A power-aware SWDR cell for reducing cache write power.

Yen-Jen Chang, Chia-Lin Yang, Feipei Lai

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

2002

Using Intel Streaming SIMD Extensions for 3D Geometry Processing.

Wan-Chun Ma, Chia-Lin Yang

Proceedings of the Advances in Multimedia Information Processing, 2002

A Programmable Memory Hierarchy for Prefetching Linked Data Structures.

Chia-Lin Yang, Alvin R. Lebeck

Proceedings of the High Performance Computing, 4th International Symposium, 2002

2000

Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions.

Chia-Lin Yang, Barton Sano, Alvin R. Lebeck

IEEE Trans. Computers, 2000

Push vs. pull: data movement for linked data structures.

Chia-Lin Yang, Alvin R. Lebeck

Proceedings of the 14th international conference on Supercomputing, 2000

1999

Annotated Memory References: A Mechanism for Informed Cache Management.

Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, Mithuna Thottethodi

Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998

Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications.

Chia-Lin Yang, Barton Sano, Alvin R. Lebeck

Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998